JPS6132133A - Display information processor - Google Patents

Abstract

PURPOSE:To distinguish accurately a window area to be edited from an area at the outside of the window by writing at least 1-bit data inverting a data before displaying the window as to each picture element data of a two-dimension area set to the window. CONSTITUTION:A data fixed mode and a logical inversion operating mode are set to a DMAP in a display inverting processing routine, values of registers BCA, BCX, BCY and a fixed value XM are set respectively to registers RSA, RXB, RYL and RXM to generate a DMA request thereby awaiting the end of DMA transfer. A start address, lateral length and longitudinal length of the window are stored respectively to the registers BCA, BCX and BCY. Then in executing the display inverting processing, since the data inverted at each bit of the original data is written to each memory as to the two-dimension memory area corresponding to the window area, the window area and other areas are distinguished.

Description

[Detailed Description of the Invention] ■Field of the Invention The present invention relates to information processing that processes two-dimensional or more dimensional information including information such as figures, photographic images, two characters, etc., and particularly to displaying that information as visible information. The present invention relates to display information processing that processes display information in response to instructions from an operator.

(2) Conventional Technology When editing two-dimensional information such as graphics, the information is usually displayed on a cathode ray tube display (CRT), and data processing of the displayed information is performed in accordance with instructions from an operator. When processing two-dimensional information, it is necessary to specify a two-dimensional processing area on memory.

In that case, in order to match the visible two-dimensional area that the operator desires to process with the memory address of the processing data corresponding to each pixel in that area, a rectangular or two-dimensional window is displayed, and inside the device Preferably, the memory area is specified by the coordinates of the window.

When performing this type of processing, conventionally, a rectangular pattern of four line segments is displayed on the display surface, and this is used as a window (usually called a block cursor). When setting the display of this type of window, you generally position the cursor at the top left corner of the window, then set the cursor position to the bottom right coordinates of the window to display the window at those coordinates, and resize it. In adjustment mode, the lower right coordinates of the window can be updated every time the cursor moves.

However, with this type of window, two-dimensional information cannot be edited accurately. In other words, in this type of window, the window line is displayed superimposed on the display pattern, so the display pattern cannot be seen at the position of the window line, and whether the position of the window line belongs to the window area or is outside the window area. It cannot be determined whether the device belongs to the device unless you actually execute the process or refer to the instruction manual for each device. Moreover, in order to display the line segment of the window on the same memory as the image data in order to display this type of window, the window must be displayed in such a way that the image data at the position where the line segment is displayed is not destroyed. It is necessary to first save the data at that location to a special memory, and then restore the saved data to the display memory after erasing the window, which requires extra memory for saving data.

■Object of the Invention The first object of the present invention is to provide a display information processing device that can accurately distinguish between a window area to be subjected to one editing process and an area outside the window, and to save data for window display. The second purpose is to eliminate the need for memory, and the third purpose is to process window display/erasure in a short time.

■Structure of the Invention In order to achieve the above object, in the present invention, at least one bit is written for each pixel data of a two-dimensional area set in the window, and data that is the inverted data before displaying the window is written into the window. express. In other words,
In the simplest black-and-white display in which one bit is assigned to each pixel, data in the window area is rewritten to reverse the black and white of each pixel before displaying it. When performing gradation expression, it is sufficient to write the complement of the gradation data of each pixel into the memory of the window area, and when performing color display, the window area is written in the complementary color of the color before displaying it. By rewriting the data so that the window area and other areas are easily distinguished.

According to this, special lines unlike conventional windows are not displayed, so the window area and other areas can be distinguished without a single pixel error, and accurate editing becomes possible. Moreover, according to this, the display data is simply inverted and not destroyed, so even if you do not save the data in the window area, you can obtain the original data by inverting the data in that area again. No data saving memory is required.

However, in order to display this type of window, simply displaying or erasing the window requires inversion processing for all display memory data in a designated two-dimensional area, resulting in an enormous amount of processing.

Performing this type of processing using an ordinary microprocessor takes a very long time. Therefore, in a preferred embodiment of the present invention, a special MA (direct MA) performs predetermined logical processing (inversion processing in the case of window display) on data read from the transfer source and writes the processed data to the transfer destination.
The above window display is realized using a memory access) control device. In other words, a normal DMA control device can only perform simple data transfers, so even if a simple process like the window display above is repeated, DMA processing cannot be performed if data processing is involved in the process. This type of processing is possible with a DMA control device that performs logical processing during data transfer.

Further, in a more preferred embodiment of the present invention, a two-dimensional processing DMA control device is used that automatically generates two-dimensional address information according to the first dimension size and second dimension size of a preset processing area.

As a result, not only window display, but also processing such as moving data in the window area to an arbitrary position and scrolling can be performed at high speed without intervening a central processing unit (CPU) during the processing.

Example Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of a DMA control device used in a display information processing device to be described later. Briefly speaking, this DMA control device differs from a normal DMA control device in that it transfers data in a two-dimensional area and can process data during data transfer.

This will be explained with reference to FIG. This DMA control device has
8 data lines, 2
0 address lines, several DMA request signal lines D
REQ (DMA request), several DMA response signals DA CK (DMA acknowledge), hold request signal line HRQ (hold request) to the central processing unit, hold confirmation signal line HLDA (hold acknowledge) from the central processing unit , the reset signal line RESET.

Clock signal line CLK, processing end signal line EOP
(end of process) and other signal lines are provided.

When this DMA control device is actually incorporated into a system, each of the above signal lines is connected to a path line of the system.

When setting the operation mode, control parameters, etc. to this DMA control device, the DMA control device uses the human output buffer BF.
2, various information is taken in from the data line.

In that case, the command control circuit MCMC determines what the data means based on the information input to the address line at that time.

Command data specifying the operation mode etc. is held in the command register RCM. In this example, the operation modes of the DMA control device include data movement/data fixing mode, calculation mode/non-calculation mode, etc. Data movement mode is a mode in which data input from a first address area is moved (transferred) to a second address area, and data fixation mode is a mode in which data input from a first address area is transferred to a second address area. This is a mode in which data is transferred to address area 1 (address remains unchanged). In data movement mode, the data input from the first address and the
It is possible to perform an operation on the data input from the address of and output the result. The calculation mode is a mode in which preset calculation processing is performed on input data and the result is output to the transfer destination.

In the calculation mode, specify what kind of calculation to perform. In this example, the operation modes include bit-by-bit inversion, logical sum of first data and second data, logical product of first data and second data, and logical sum of first data and second data.
Exclusive OR with data, erasure (writing zero), one rotation (bit shift), etc. are provided.

When actually transferring data, various parameters are set in addition to the operation mode. In this example, the parameters include the transfer source start address, the transfer destination start address, the length of the X coordinate (the number of bytes), the length of the Y coordinate (the number of lines) (in the case of rotation, an integral multiple of 8), and the output device (display There are five memory amounts (number of bytes) per line determined by the configuration of the device. These parameters are
Transfer source start address register R3A, transfer destination start address register RDA, byte number setting value register RXB, line number setting value register R'l'L, respectively.
, and stored in the line byte setting value register RXM.

Address information for data transfer is output from four counters SS, SI, DS and DI. Counters SI and DI are 16-bit counters, SS
and DS is a 4-bit counter. One address information (20 bits) is generated by one index address counter SI or DI and one segment address counter SS or DS. The index address counters S and DI are incremented or decremented each time a transfer is performed, and when they overflow or underflow and a carry is output, the segment address counter SS or DS is incremented or decremented.

The X counter CNX and the Y counter CNY count the number of times the X and Y coordinates of the two-dimensional area to be transferred are updated, respectively.

The timing and control circuit TMC controls the processing timing of the entire DMA control device.

Next, an outline of the processing operation of the DMA control device shown in FIG. 1 will be explained with reference to FIGS. 2a, 2b, and 2c.

First, set the operating mode, commands, various parameters, etc. Here, when the data movement mode, that is, the mode in which data is transferred between mutually different addresses, is set, the presence or absence of area overlap is then checked.

In other words, the order of addresses in which data is transferred can generally be updated from small addresses to large addresses, or vice versa, but the If there is an overlapping part between them, depending on the update direction, a memory area may be set as the transfer source after being set as the transfer destination, and in that case, the contents of the changed data are transferred again Therefore, the contents of the memory to which the data was transferred will become abnormal.

Therefore, if there is an overlap between transfer memory areas, the direction of the overlap is determined and flags FX and FY are set according to the result. If the transfer destination address is larger than the transfer source address in the first dimension (X-axis direction), that is, if the transfer destination area is on the right side of the transfer source area on the display screen, the flag FX is set to n 1 n. If not, set flag FX to II O11. Also, if the destination address is larger than the source address in the second dimension (Y-axis direction), that is, if the destination area is lower than the source area on the display screen, the flag FY is set to '1. ”, otherwise flag F
Set II OII to Y. Note that if there is no overlap in the areas, both flags FX and FY are set to tr Otr.

If flags FX and FY are both II OII, the contents of the transfer source start address register R3A are preset to the transfer source segment address counter SS and transfer source index address counter SI, and the contents of the transfer source start address register R3A are preset to the transfer destination segment address counter DS and transfer destination index address counter SI. The contents of the transfer destination start address register RDA (the coordinates of the upper left end of the area on the display screen) are preset in DI. Similarly, flag FX is II 1 jl and FY is 710
In the case of H, the byte number setting value register RX is added to the contents of the transfer source start address register R3A in SS+S■.
The result of adding the contents of B is preset, and the result of adding the contents of the transfer destination start address register RDA and the contents of the byte number setting value register RXB is preset in DS+DI (the upper right coordinate of the area on the display screen). Flag F
If X is tp Opp and FY is IT I II, then
Preset the result of multiplying SS+SI by the contents of the line byte setting value register RXM and the contents of the line number setting value register RYL and adding the contents of the transfer source start address register R8A (lower left coordinate of the area on the display screen). Then, set line byte setting value register R to DS+DI.
The result of multiplying the contents of XM by the contents of line number setting value register RYL and adding the contents of transfer destination start address register RDA is preset. Otherwise, if flags FX and FY are both n 1 n, SS
Preset the result of multiplying +SI by the contents of line byte setting value register RXM and the contents of line number setting value register RYL, adding the contents of byte number setting value register RXB, and the contents of transfer source start address register R3A. Then, as a result of multiplying DS+DI by the contents of the line byte setting value register RXM and the contents of the line number setting value register RYL, the byte number setting value register RXB
contents, and transfer destination start address register RDA
Preset the result of adding the contents of.

A request for DMA transfer (e.g. from the central processing unit CPU)
If so, proceed to the next process. However, if the channel is masked in advance, only that request is stored.

If the mask is released, the DMA acknowledge signal D
It outputs ACK to the device that requested the transfer, and then outputs a hold request signal HRQ to the central processing unit. When the central processing unit receives the hold request HRQ, the central processing unit releases the system bus after finishing the process currently being executed.
A hold acknowledge signal HLDA is output to the DMA control device. After this, the DMA control device controls the system bus to perform predetermined data transfer.

First, counter CNX is set to byte number setting value register RXB.
The contents of the line number setting value register RYL are preset to the counter CNY.

Address information generated from the contents of the transfer source segment address counter SS and transfer source index address counter SI is output to the address line of the system bus via the multiplexer & output buffer BFI, and at the same time a memory read strobe signal (not shown) is output to the address line of the system bus. ) and output
Read the contents of the transfer source memory. Here, the data appearing on the data line is taken into the DMA control unit via the input/output buffer BF2, and is sent to the logic operation unit ALU.
Latch with.

When there is one address, that is, the transfer source address and the transfer destination address are the same, and the operation mode is set, the data latched in the logical operation unit ALU is transferred to the ALU according to the type of operation mode. The calculation is performed internally, and the result is also held in the ALU.

Then, the contents of the transfer source counter SS+SI are outputted to the address line, the data held in the logical operation unit ALU is outputted to the data line, and a memory write strobe signal (not shown) is outputted to write the contents of the memory. rewrite.

Operation modes when the data transfer source address and data transfer destination address are different are divided into two groups.

One is a mode in which the contents of the logical operation unit ALU are inverted, erased, and logically operated with a predetermined value, and the other is a mode in which the contents of the logical operation unit ALU and the transfer destination address (DS+DI ) is a mode in which logical operations are performed on data stored in In either mode, the results are stored in the logic unit ALU. Then, it outputs the transfer destination address (DS+DI) to the address line, outputs the contents of the logic operation unit ALU to the data line, outputs the data write strobe signal to the system bus, and rewrites the contents of the memory with the operation result. .

When one transfer process is completed, the contents of the counter CNX are decremented. As a result, if the contents of the counter CNX are 0 or more, the contents of the counters SS, SI, DS, and DI are updated according to the state of the flag FX. If the flag FX is II OP+, the index address counters SI and DI are incremented, and the FX is II 1.
# then decrement them. If index address counters SI and DI overflow (or underflow) at that time, the values of segment address counters SS and DS are updated (incremented or decremented), respectively.

If the result of decrementing the counter CNX is negative, the contents of the byte number setting value register RXB are reset to the counter CNX, the counter cNY is decremented, and the address counter SS is set according to the states of the flags FX and FY.
, SI, DS and DI are reset. Flag F
If both X and FY are 0'', add the contents of the line byte setting value register RXM to the counter SS middle SI, subtract the contents of the byte number setting value register RXB, and add the contents of RXM to the counter DS+D! and subtracts the contents of RXB.Similarly, when flag FX is II 1 jl, FY
When is NOII, the contents of register RXB and register RXM are added to counter SS-SI, and the contents of RXB and RXM are also added to counter DS+DI. When flag FX is II OII and FY is 1'', the contents of register RXB and register RXM are subtracted from the contents of counter SS+SI, and the contents of register RXM are subtracted from the contents of counter SS+SI.
From the contents of DI, the contents of register RXB and register RXM
Subtract the contents of. Other than that, that is, flag FX and FY
If both are 1'', register RX in counter SS and SI
Add the contents of B, subtract the contents of register RXM,
Add the contents of register RXB to counter DS+DI and subtract the contents of register RXM.

In other words, in a normal display device where the memory address increases from left to right and from top to bottom on the two-dimensional display surface, the direction in which the address is updated is the flag FX.
and FY are both n Ou, the direction is from left to right and from top to bottom on the display screen, and the flag FX is I
When I I II and FY is II OEl, the direction is from right to left and from top to bottom on the display screen, and when the flag FX is "O" and FY is II I II (7), it is on the display screen. is a direction from left to right and from bottom to top, and when flags FX and FY are both set to II III, it is a direction from right to left and from bottom to top on the display screen.

If the result of decrementing the counter CNX becomes negative and the result of decrementing the counter CNY becomes negative, it means that data transfer for all areas has been completed.
The hold request signal HRQ is released, the system bus is released for the central processing unit, and the initial state is returned.

FIG. 3 shows a - format display information processing device.

This will be explained with reference to FIG. This display information processing device is equipped with the DMA control device shown in FIG. 1 as a direct memory access unit DMAP. In addition to the microprocessor MPU and the direct memory access unit DMAP, the system bus of this device includes an address decoder ADD, a main memory RAM1, a read-only memory ROMI, an I10 port IOP, a bitmap memory RAM2. Character memory RAM 3
, external memory interface IFI, scanner interface IF2. A keyboard unit, display signal synthesis unit DSPU, etc. are connected.

The display signal synthesis unit DSPU generates a signal for displaying a predetermined image on the cathode ray tube display unit CRTU. This signal includes data corresponding to each pixel written in bitmap memory RAM2 and character memory RAM2.
It is generated by ORing with pixel data corresponding to the character code written in 3. In this example, pixel data of a large number of character patterns are written in advance in the character generator ROM2, and when the character memory RAM3 outputs predetermined character code data, the corresponding character pattern data is output to the display signal synthesis unit DSPU. . Note that the CRT display unit CRTU is a color display.

A floppy disk unit FDU and a laser disk unit RDU are connected to the external memory interface IFI, and an image scanner IMS is connected to the scanner interface IF2.

FIG. 4 shows the configuration of the bitmap memory RAM2 of FIG. 3. Please refer to FIG. This memory RAM2 has four banks of read/write memory of 512 bytes each. The system bus connected to the microprocessor MPU is configured so that one of four banks can be connected. However, the display signal synthesis unit DSPU has 4
You can access two banks at the same time.

Memory address of bitmap memory RAM2 and CRT
The correspondence relationship with the information displayed on the display unit CRTU will be explained with reference to FIGS. 9 and 10. In this example, each data bit in the bitmap memory is divided into 2048
204g of two-dimensional coordinates are assigned to each pixel, of which an area of 1024 x 768 can be displayed on the display screen of the CRT display unit CRTU at a time. 1
Each bit of byte data corresponds to 8 consecutive pixels in the horizontal direction, and one line of pixels in the horizontal direction corresponds to 256 bytes of memory with consecutive addresses.

Note that an area of several pixels in the horizontal direction (ΔX) and several pixels in the vertical direction (Δy) among the two-dimensional coordinates of 2048 x 2048 is allocated as a non-display area for scrolling, which will be described later.

Pixel data at each coordinate is composed of 4-bit data obtained from each memory bank.

The color of the pixel displayed on the CRT display unit CRTU is determined according to the configuration of this 4-bit data. In this embodiment, the complementary relationship of 4-bit data and the complementary color relationship of display colors match. In other words, when predetermined 4-bit data is displayed and the data is rewritten into a complemented version, the complementary color of the previously displayed color will be displayed.

FIG. 5 schematically shows the operation of the microprocessors MP and U shown in FIG. 3 when editing data. When processing starts, initial settings are made and a key human power check is performed. When there is an input from the keyboard unit KEY, the type is determined,
Proceed to the appropriate process. In this example, there are specifically 11 types of commands. The function of each command is as follows.

KO: To call up image data that has been previously stored on the disk 1: To save data on the memory (RAM2.'RAM3) to the disk 2: Setting the amount of movement of the cursor, etc. when operating the cursor keys, flags Set F2.

K3: Instructions to move the cursor, select a 4-niblock cursor (window) to move up, down, left or right, select one of the three and set flag F4 accordingly to display a 5-niblock cursor /Erase 6: Display data and/or block cursor status setting instruction, select processing according to the status of flags F7 and F8 7: Specify window size setting mode, set flag F7 8: Window movement mode Specify, set flag F8 to 9:
Display data editing instructions Two-character input process other than the above Next, we will discuss the features of the device shown in FIG. 3, which are shown as subroutines in FIG. "Edit" will be explained in detail. An outline of these processes is given in Section 6a.
It is shown in FIGS.

When 5 is specified in the command, flag F5 is checked. Flag F5 is set to II I II when the block cursor or window is displayed, and is set to HOII otherwise.

Note that in this specification, symbols (flags, registers, etc.) with symbols enclosed in parentheses, such as F5 (F4) shown in Figure 6c, indicate that there are multiple symbols, and the symbol is selected by the parameter in the parentheses. This means that the processed items are subject to processing. That is, in command 5, processing is performed on the window previously selected in command 4.

If flag F5 is no'u, execute the "window display set" subroutine, if #l 171, execute the "window display clear" subroutine, and in either case, after processing, flag F5 is executed.
Invert the state of .

In the "window display set" subroutine, flag F5 is checked, and if it is O, memory banks 1, 2, 3 and 4 are set.
For each of the "display inversion processing" subroutine and "
Execute the window identification mark display subroutine. In "display inversion processing", data fixing mode and logical inversion operation mode are set for direct memory access unit DMAP, and registers R8A, RXB, RYL, and RXM are set to registers BCA, BCX, and BC, respectively.
It sets the values of Y and the fixed value XM, generates a DMA request, and waits for the DMA transfer to complete.

Registers BCA, BCX, and BCY respectively contain the start address of the window (upper left corner), the horizontal length of the window,
and the vertical length of the window (the number of lines) are stored. Therefore, when the "display inversion process" is executed, data obtained by inverting the original data bit by bit is written into each memory in the two-dimensional memory area corresponding to the window area. In other words, in the case of the simplest black/white display, the two-dimensional area set in the window is rewritten with display content that is the black and white inversion of the previous display content.

FIG. 7 shows an example of a state in which the window is displayed. In FIG. 7, BCI, BO2 and BO3 are windows, and PL, P2
and P3 are arbitrary display pattern data. Referring to FIG. 7, although no lines are drawn in the window area, it is clear that the window area and other areas can be distinguished. Moreover, since no lines are drawn, the window area and other areas can be reliably identified without a single pixel error.

"Window identification mark display J is a process that, when multiple windows are displayed, displays the distinction between each window within the window. Specifically, the first window has one horizontal line, the second Two horizontal lines are displayed on each window, and three horizontal lines are displayed on the third window.

Note that these horizontal lines are displayed by inverting the data before displaying them, as in the case of windows. See Figure 6e.

If flag F4 is 2 or more (selects the third window), B C
Write data obtained by inverting the contents bit by bit to a 5-byte memory whose starting address is A 1 N x + (N3yX X M). If flag F4 is 1 or more (selecting the second window or third window), further BC
5 with A+Nx+ (N2yXXM) as the starting address
Write those inverted data to the byte memory, and if flag F4 is 0 or more (select the first window, second window, or third window), further write BCA+Nx+(NlyXX
The inverted data is written to a 5-byte memory whose starting address is M).

That is, for example, when the third window BC3 is selected, three lines (marks) Mj, M2 are displayed as shown in FIG.
and M3 are displayed in the upper left corner of the window.

If it is the second window, lines M2 and Ml are displayed, and if it is the first window, only line M1 is displayed.

In the "window display clear" subroutine, flag F5 is
1'', it is set to u On, each memory bank 1, 2, 3, and 4 is selected, and ``window identification mark display'' and ``display inversion processing'' are executed, respectively. In other words, the process is the opposite of the "window display set" subroutine. Therefore, when the "window display set" subroutine is executed, the selected window is displayed with its mark, and when the "window display clear" subroutine is executed, the selected window is erased.

When 6 is specified in the command, "display processing" is executed. Flag F by 7 on the command before this is indicated.
If 7 is set to a value other than 0, the display window is enlarged or reduced. In addition, when displaying the window for the first time,
A window is displayed with a predetermined initial size. Flag F
If 7 is n 1 n, move (update) the coordinates of the bottom edge of the window below the current level, and if flag F7 is +r 2 n, move the coordinates of the bottom edge of the window above the current level. However, if flag F7 is II 31+, move the coordinates of the right edge of the window to the right from the current position, and if flag F7 is +l 4 IT, move the coordinates of the left edge of the window to the left from the current position. . The movement amount N is 1 if flag F2 is u On, and F2 is II
I If it is 11, set it to 10. When performing this process, first execute the "window display clear" subroutine to erase the displayed window, update the value of the window parameter BCY or BOX, and then execute the "window display set" subroutine again. do.

If the flag F8 is set to a value other than 0 by the command 8 before the command 6 is specified, the following operation occurs depending on the contents of the flag F8. If the flag F8 is 1, a "window movement" subroutine is executed, and only the currently displayed window (the entire window) is moved on the screen. If the flag F8 is 2, a "window/data movement" subroutine is executed, and the window being displayed and the display data located in the window area are moved to the designated position. Also, if flag F8 is 3, "data movement"
Execute the subroutine and move (scroll) only the displayed data.

In the "window movement" subroutine, first the flag F5 is checked, and if it is pr 1 n, the next movement process is performed. In the movement process, execute the "window display clear" subroutine to erase the displayed window, update the parameter BCA (start address) of that window, and then execute the "window display set" subroutine to display the window again. do. In other words, the data displayed on the screen of the CRT display unit CRTU remains unchanged, and only the position of the window moves in accordance with the designated direction. Depending on whether the direction of movement is up, down, left or right, the window parameter BCA is updated as follows.

If the moving direction is upward, the result of multiplying the number of bytes of one line XM by a predetermined number N is subtracted from the contents of register BCA. Similarly, if the direction of movement is down, the result of multiplying XM by a predetermined value N is added to the contents of register BCA, and if the direction of movement is left, the value of predetermined value N is subtracted from the contents of registers BCA, A. , if the moving direction is right, a predetermined value N is added to the contents of register BCA.

The predetermined value N is an arbitrary value or a value of 1 or 10 depending on the flag F2.

In the "window/data movement" subroutine, flag F5 is first checked and if it is +71 II, the process proceeds to the next step. If the moving direction is upward, a value obtained by multiplying the number of bytes of one line XM by a predetermined value N is subtracted from the contents of register BCA, and the value is stored in register BCD. Cash register B
The CD is for storing the start address of the data transfer destination of each window. Similarly, if the direction of movement is down,
The value obtained by multiplying XM by N is added to the contents of register BCA and stored in register BCD. If the movement direction is left, the value obtained by subtracting N from the contents of register BCA is stored in register BCD.
If the movement direction is right, the value obtained by adding N to the contents of register BCA is stored in register BCD. And r
DMA data movement" subroutine is executed.

In the ``rDMA data movement'' subroutine, the DMA
After setting the control device as follows, issue a DMA request and wait for the DMA transfer to finish. The operation mode is set to data movement mode and OR operation mode. and registers R5A and RDA.

Register BC in RXB, RYL and RXM, respectively.
Set the values of A, BCD, BCX, BCY and predetermined value XM.

When the DMA issues a request with these settings, the DMA
The control device first reads the transfer source data and latches it, then reads the transfer destination data, performs a logical OR operation between it and the latched data, and then uses the result as the transfer destination address. The process of storing in memory is performed for the entire two-dimensional area of the window. That is, in the two-dimensional area to which the window is moved, the data before the movement and the data that was at the window position before the movement are displayed.

When "rDMA data movement" is completed, set the contents of register BCD to register BCA, and then "set window display".
Execute a subroutine. As a result, the window will be displayed again at the same location (transfer destination) as the moved data.

In the "data movement" subroutine, flag F5
The contents of (1, 2, 3) are saved in a predetermined memory before proceeding to the next process. Execute the "window display clear" subroutine for each window that is currently displayed to erase the window. Next, the direction of data movement (scrolling) is checked, and the contents of registers R8A and RDA are set as follows according to the result.

Upward scroll RS A: Am1n RDA: Am1n ten ((YM-N)XXM) Downward scroll R8A: Am1n+((YM-N)XXM) RDA
: Am1n+(YM'XXM) Scroll leftward RS A: Am1n RDA: Am1n10 (XM+N) Scroll rightward R8A: Am1n+(XM-N) RDA: Am1n10XM However, the minimum address of All1in S RAM 2 YM: Maximum value of Y coordinate of display memory N: Transfer distance (ΔX or Δy in FIG. 9) Further, predetermined values XM,
YM and XM are set, the operation mode of the DMA controller is set to data movement mode and non-operation mode, and a DMA request is issued.

When DMA transfer is performed as a result, the data in the bitmap memory RAM2 moves up, down, left, or right by N on the two-dimensional coordinates shown in FIG. The data displayed on the screen is updated (scrolled).

Next, load the saved data into flag F5 (1', 2.3), and for each of them, if the window display is set, execute the window display set subroutine and set the window. Redisplay.

Next, "display data editing" will be explained. In this process, an editing mode is first specified, and processing is performed according to the result. In this example, "edit reversal processing", "edit deletion processing", "edit extraction processing", "edit movement processing", and "edit exchange processing" can be executed.

In the "edit reversal process", the display data of that portion of the two-dimensional area where the window is displayed is inverted bit by bit. In this example, the "window display clear" subroutine is executed, the "display inversion processing" subroutine is executed for each of memory banks 1, 2, 3, and 4, and the "window display set j subroutine is executed to perform this processing." ing.

In the "edit/delete process", the display data of that part of the two-dimensional area where the window is displayed is deleted. First, execute the "window display clear" subroutine to erase the window, execute "display erase processing" for each of memory banks 1, 2, 3, and 4 to clear the memory contents, and then select "window display set". Execute the subroutine and redisplay the window.

In "display erasure processing", data fixing mode and erasure operation processing mode are set as the operation modes of the DMA control device, and registers BCA, BCX, BCY and a predetermined value
Set the value of M and issue a DMA request. In this state D
When MA transfer is performed, registers BCA, BCX and BC
All 0s are written into the memory of the two-dimensional area designated by Y, that is, the area where the window was displayed.

In the "edit extraction process", display data corresponding to the area where the window is displayed is stored in the laser disk unit RDU. First, wait for the file name to be input, and once it is input, execute the "window display clear" subroutine to clear the window and display the display data at the address corresponding to the window area in memory banks 1, 2, 3, and 4. , are stored in the laser disk unit RDU together with the input file name. Once the data has been stored, the ``Set Window Display'' subroutine is executed to display the window again.

In the "edit movement process", a process is performed to move the data located in the currently selected window position to the position of another window. First, wait for the destination window to be specified.

The destination window is stored in flag F4'b. To use the subroutine, the contents of flag F4 and F4b are exchanged, and the "window display clear" subroutine is executed to erase the destination window. Next, in order to match the size of the source window and the destination window, register B OX (
Store the contents of F4b) in register BOX (F4), and store the contents of register BCY (F4b) in register B
Store it in CY (, F4) and execute the "window display set" subroutine. When you do this, the size of the window you specified as the data destination will match the size of the source window.

At this point, you can change the position of the selected window, that is, the window to which you want to move. When a movement start instruction is given, a ``window display clear'' subroutine is executed, the contents of the flag F4 and the flag F4b are exchanged and returned to their original values, and the ``window display clear'' subroutine is executed again. This erases both windows. Next, DMA
Set the control device as follows. As the operation mode, a data movement mode and an OR operation mode are set. And each register R8A, RDA, RXB, ,R
Register BCA (F4) for YL and RXM, respectively.
, BCA (F4b), BCX (F4), BcY (F4)
, and a predetermined value XM.

In this state, each of memory banks 1, 2, 3, and 4 is selected and a DMA request is issued for each. When this is done, the display data at the source window position overlaps the data at the destination window position (logical OR). When the data movement is completed, the "window display set" subroutine is executed for each of the transfer source window and the transfer destination window to display the windows again.

In the "edit exchange process", display data at the currently displayed (selected) window position and display data at another window position are exchanged. First, wait for the second window to be specified. As in the previous case, the contents of flag F4 and F
4b, execute the "window display clear" subroutine to erase the second window, adjust the second window size parameters (BCX, BCY) 3 to the values of the first window, and
The window display set subroutine is executed to display the second window again.

Waits for an instruction to start the data exchange process, and when that instruction is received,
Erase the two windows. Then, the display data of the first window area is saved to a predetermined area of the main memory RAM1, and "display erasure processing" is executed for each of memory banks 1, 2, 3, and 4 of the bitmap memory RAM2, and the display data of the first window area is saved. Clear the display data in the window area. Then DM as follows
Set the A control device and execute "rDMA transfer". The operation mode is set to data movement mode and non-calculation mode,
Each register R8A, RDA, RXB, RYL and RX
M d, registers BCA (F4b) and BCA respectively
(F4), BCX (F4), BCY (F4), and the predetermined value XM are set. When DMA transfer is performed in this state, the same data as the display data in the second window area is stored (displayed) in the first window area as the movement destination.

Next, flags F4 and F4b are exchanged again, and "display erasure processing" is performed for each of memory banks 1, 2, 3, and 4.
is executed to erase the display data in the second window area. Furthermore, the DMA control device is set as follows to perform rDMA transfer. The operation mode is data movement mode and non-operation mode, and registers R8A, RDA, RXB, RYI
4 and RXM, display data save address (first
RAMI address where window data was saved), registers BCA (F4), BCX (F4), BCY (F4),
and set the value of the predetermined value XM. When a DMA request is issued in this state, the display data of the first window area saved in the main memory RAM1 is transferred to the second window area. Then, the "window display set" subroutine is executed for the first window and the second window, and the two windows are redisplayed.

■Effects As described above, according to the present invention, windows are displayed by inverting display data, so window areas and other areas can be accurately distinguished without a single pixel error. Since the data is not destroyed, there is no need to prepare a special memory for saving data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a DMA control device. FIGS. 2a, 2b, and 2c are flowcharts showing the general operation of the MA control device shown in FIG. 1. FIG. 3 is a block diagram showing a -type display information processing device using the DMA control device shown in FIG. FIG. 4 is a block diagram schematically showing the bitmap memory RAM2 of FIG. 3. FIG. 5 is a flowchart showing the general operation of the microprocessor MPU shown in FIG. Figures 6a, 6b, 6c, 6d, 6e,
Figure 6f, Figure 6g, Figure 6h, Figure 61, Figure 6j,
Figure 6, Figure 6Q, Figure 6m. 6n and 60 are flowcharts showing details of the process shown in FIG. 5. FIG. 7 is a front view showing an example of the display surface of the CRT display unit CRTU shown in FIG. 3, and FIG. 8 is a front view showing a part of FIG. 7 in an enlarged manner. 9 and 10 are plan views showing the correspondence between two-dimensional coordinates of display pixel data and memory addresses. SS, SI, DS, DI: Counter BF2: Input/output buffer ALU: Logic operation unit TMC,: Timing & control circuit BCI, BO
2, BO2 block cursor (window: PI, P2.P3
Two display patterns C5R: Cursor CRTU: CR
T Display unit (surface display means) RAM2: Bitmap memory (display memory means) DSPU: Display signal generation unit (display signal generation means) KEY: Keyboard unit (operation instruction switch means)

Claims (11)

[Claims] (1) Surface display means for displaying two-dimensional information; Display memory means comprising a memory that corresponds one-to-one with the state of each display pixel of the surface display means; Reading the contents of the memory of the display memory means; display signal generation means for generating a signal to be applied to the surface display means; operation instruction switch means; Set a two-dimensional area of the size, invert the contents of the memory corresponding to the area by at least 1 bit for each pixel,
A display information processing device comprising: electronic control means for expressing a window thereby; (2) The electronic control means includes a DMA control device that performs predetermined logical processing on the data read from the transfer source and then sends the data to the transfer destination.
The display information processing device described in Section 1. (3) The DMA control device includes a first counter that counts a value corresponding to the address update amount of the first dimension of the transfer data area, and a second counter that counts a value corresponding to the address update amount of the second dimension of the transfer data area. Two-dimensional processing DMA with two counters
The display information processing device according to claim (2), which is a device. (4) The surface display means is a color display, and the electronic control means sets the color of the display pixels in the window area to a complementary color to the color before setting that area as a window. The display information processing device described in Section 1. (5) When the electronic control means receives a window position movement instruction or a window size update instruction from the operation instruction switch means, the electronic control means inverts the contents of the data corresponding to the window area, updates the window parameters, and Claim No. 3, wherein the content of the data corresponding to the window area according to the parameter is inverted.
1) The display information processing device described in section 1). (6) The electronic control means updates the position of the window, moves data corresponding to the window area and updates the position of the window, and fixes the position of the window in accordance with the instruction from the operation instruction switch means. A display information processing apparatus according to claim 1, wherein data movement of display memory means is performed. (7) When moving data in a predetermined two-dimensional area to another two-dimensional area, if there is an overlap between those areas, the electronic control means determines the direction of the overlap, and according to the result,
The display information processing device according to claim 1, wherein the update direction of the data transfer address is selected. (8) The display memory means includes, in addition to the memory corresponding to the pixels displayed on the surface display means, an auxiliary memory of at least one bit each at an address adjacent to the edge of the two-dimensional display area, 2. The display information processing device according to claim 1, wherein the data is transferred and scrolled using the auxiliary memory. (9) The electronic control means displays a plurality of windows, and moves data from one window area to the other window area and exchanges data between the window areas in accordance with instructions from the operation instruction switch means. A display information processing device according to claim 1, which performs at least one of the following. (10) The display information processing device according to claim (9), wherein, when displaying a plurality of windows, the electronic control means displays a different type of identification mark for each window. (11) The display memory means includes a bitmap memory that corresponds to each display pixel one-to-one, and a code memory that stores code data corresponding to a predetermined pattern, and the display signal generation means includes a bitmap memory that corresponds to each display pixel one to one, and a code memory that stores code data corresponding to a predetermined pattern. Claims (1), (2), (3), and (1) display the contents, and the pattern and pixel data output according to the contents of the code memory on a surface display. Section 4), Section (5),
The display information processing device according to item (6), item (7), item (8), item (9), or item (10).