JPS6130886A - Correcting device for picture memory - Google Patents

Abstract

PURPOSE:To improve an arithmetic speed by making it possible to access to picture memory through a central processing unit only during a period of reading picture element data. CONSTITUTION:A controller 2 outputs an address signal for reading through a terminal 2R, and said signal is sequentially fetched into a memory 1. Afterwards built-up picture element data in a read address is read out in a lump. The memory 1 shares buffer memory of a computer. In terms of a central processing unit 8', the memory 1 can be accessed only when a control pulse generated by the controller 2 is supplied to an input port 8a and is at a high level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image memory correction device, and in particular to a correction device for correcting pixel data to be read from an image memory, part or all of which is shared as a computer buffer memory. The present invention relates to a correction device for outputting.

2. Description of the Related Art Conventionally, a digital audio signal obtained by digital pulse modulation such as pulse code modulation (PCM) is added with a digital video signal containing auxiliary information such as a color still image, and is recorded on a disc-shaped recording medium (hereinafter referred to as "disc-shaped recording medium"). Digital audio discs are known in which data is recorded in chronological order as a series of intermittent pits on a disc (referred to as a "disc"). In such a digital audio disc, a green signal is read by detecting a change in the light intensity of reflected light or transmitted light from the disc, or a change in an electrostatic capacitor formed between the disc and an electrode with a reproduction amount of 1. will be played.

This digital audio disc playback system includes:
In addition to the digital audio signal reproducing circuit, the above-mentioned digital video signal reproducing circuit is also installed. Furthermore, within this digital video signal reproducing circuit, there is a memory circuit (image memory) for storing and reading out digital video signals (pixel data), a control circuit for accessing this image memory, and a control circuit for storing and reading out digital video signals (pixel data). An encoder that outputs a composite video signal of a predetermined standard TV gene format after passing the data through a D/A converter, and various synchronization signals (e.g. vertical synchronization signal, horizontal synchronization signal, etc.) supplied to this encoder. It is comprised of a signal generator that generates memory control pulses for accessing the image memory, and other components.

On the other hand, as proposed by the present applicant in Japanese Patent Application No. 58-124217, etc., the above-mentioned digital audio disk contains control program signal data for interactive playback with a personal computer, etc. together with a digital video signal. etc. are recorded. When playing such a disc, a device with a judgment function such as a personal computer is connected to the disc playback device.

In such a system, it is preferable to have the image memory in the disk playback device coexist as a data storage section of the personal computer in terms of simplifying the circuit configuration and reducing the cost.

Problems to be Solved by the Invention However, in a system in which the image memory as described above coexists with the image storage section and the data storage section, or in a system in which pixel data itself is numerically processed by a computer, the image memory ultimately Accumulated pixel data is read during the video period of the reproduced composite video signal output to the monitor device, and reproduced pixel data is written during the horizontal blanking period. However, when the computer accesses the image memory within the video signal, the accumulated pixel data Since the data cannot be read out, there is a problem in that dropouts occur in the reproduced composite video signal and noise is generated on the reproduced screen. On the other hand, if the computer accesses the image memory only during periods other than the video period, such as the horizontal blanking period or the vertical blanking period, the above dropout problem does not occur, but the access There are problems in that a waiting time is required, a large amount of information cannot be processed, and the calculation speed cannot be significantly increased.

Therefore, the present invention stores the output pixel data of the image memory in a predetermined readout period in a memory group, and allows the central processing unit (CPU) to access the image memory only during this readout period, thereby achieving the above-described problems. An object of the present invention is to provide an image memory correction device that solves the problems.

Means for Solving the Problems The present invention comprises a plurality of digital memories, memory control means, and switch circuit means. The plurality of digital memories respectively store respective pixel data read out from the image memory during a plurality of predetermined fixed periods different from each other within one vertical scanning period.

That is, each digital memory stores pixel data for a fixed period, but the stored pixel data is pixel data read out during different fixed periods. The memory control means writes pixel data for a certain period predetermined in each of the plurality of digital memories into the corresponding digital memory, and when the central processing unit accesses the image memory, it writes the pixel data for the predetermined period among the plurality of digital memories. The stored pixel data is read out from one digital memory that stores pixel data for a certain period at least one vertical scanning period before.

Furthermore, the switch circuit means outputs the output of the digital memory read by the memory control means when the image memory is accessed by the central processing unit during any one or more of a plurality of predetermined periods. The pixel data is selectively output, and when there is no access, the output pixel data of the image memory is passed through and output as is.

The access period of the image memory of the central processing unit is set to the period corresponding to the period of reading out the pixel data stored in the plurality of digital memories from the image memory. Therefore, even if pixel data cannot be read from the image memory, pixel data from at least one vertical scanning period before the access period can be read from the digital memory and used as output pixel data. Hereinafter, the present invention will be described in more detail along with examples.

Embodiment FIG. 1 shows a block system diagram of an embodiment of the apparatus of the present invention. In the figure, a memory circuit 1 corresponds to the image memory, and pixel data taken out from the controller 2 in the disk playback device (pixel data played back from the disk) is applied to the data input terminal by the latch 3. be done. Here, the above pixel data includes, for example, luminance pixel data with a quantization bit number of 8 bits obtained by sampling and quantizing a luminance signal at a sampling frequency of 9Ml-1z, and two types of color difference signals (for example, R -Y and B-Y) are separately sampled and quantized at a sampling frequency of 2.25MH7, and each has two types of color difference pixel data with a quantization bit count of 8 bits. A component encoded signal synthesized in a time-series manner using a total of six pixel data units, each consisting of four luminance pixel data and one each of two types of chrominance pixel data, passes through the latch 3 and becomes data in the memory circuit 1. Applied to the input terminal.

Here, as previously proposed by the present applicant in Japanese Patent Laid-Open No. 184883/1983, if only image information is transmitted without transmitting the horizontal blanking period etc. as luminance pixel data, -
Approximately 456 pieces per scanning line (horizontal scanning frequency 15.625
kHz), and by setting the number of effective scanning lines for one frame to 572, the product of the number of ms pixel data per scanning line and the number of effective scanning lines becomes 2. The value is extremely close and does not exceed 2I8. Therefore, the luminance pixel data is stored in four 64k RAMs per bit.
(random access memory), and since each of the two types of color difference pixel data is 1/4 of the number of luminance pixel data per number of scanning lines, it can be efficiently stored in 64k RAM, one for each pit. Can be stored well. Therefore, in order to reproduce all 8 bits of each pixel data with 8 bits of quantization bits per sample point, the memory circuit 1
is 48 (=8X (40i +i >> 64k
It consists of a RAM, and can store the above-mentioned component encoded signals for one frame in just the right amount.

Note that 6 pixel data per unit of transmission (i.e.,
It consists of four pieces of luminance pixel data and one each of two types of color difference pixel data. ) are stored at the same address in the memory circuit 1. Therefore, 456 luminance pixel data per -scanning line and two types of color difference pixel data each having N4 (=456/4) pieces are stored at 114 addresses, respectively.

The memory circuit 1 stores each pixel data (luminance pixel data) for one scanning line stored in the above-mentioned 114 addresses in total during the video period of the final output composite video signal.

3 types of pixel data (2 types of color difference pixel data) in parallel,
In addition, if the video period is divided into 114 because of the need for sequential reading, the 1H period will be divided into 141. Furthermore, in order to obtain the required resolution, each divided section (this is K
) is divided into 8, the master clock frequency is 141x8-x as shown in Figure 2 (A).
tH (where fH is the horizontal scanning frequency). The controller 2 outputs oscillation from the built-in oscillator of this master clock, divides and decodes it, and generates the output as shown in Figures 2 (B) to (F) and Figure 3 (A) (B), which will be described later. In addition to generating and outputting various pulses, the address counter generates and outputs, for example, 16-bit write address signals and read address signals, respectively.

The above write address signal is the terminal 2 of the controller 2.
From W to the above 27 K <= 141K -114)
The upper 8 bits are supplied to the driver 4U, and the lower 8 bits are supplied to the driver 4L. Further, the read address signal is taken out from the terminal 2R of the controller 2 during the video period of 114, and its upper 8 bits are sent to the driver 5.
The lower 8 bits are supplied to driver 5L.
supplied to The drivers 4U, 4L, 5U and 5L are driven only during the low level period of the pulses from the terminals 2a, 2b, 2C and 2d of the controllers 1 to 2, respectively.

First, to explain the operation during writing, the controller 2 supplies the driver 4L with a pulse as shown in FIG. The lower 8 bits of the address signal are applied to the address terminal of the memory circuit 1 via the driver 4L and the address bus. In this state, the pulse RAS supplied from the terminal 2e of the controller 2 to the memory circuit 1 falls as shown in FIG. It will be done. Next, a pulse as shown in FIG. 2(E) taken out from the terminal 2a of the controller 2 falls, and during that low level period, the driver 4U is driven, and the upper 8 bits of the write address signal are sent from the driver 4U to the memory circuit. 1 address terminal. In this state, the pulse CAS supplied from the terminal 2f of the controller 2 to the memory circuit 1 falls as shown in FIG. .

Next, the controller 2 connects to its terminal 2g as shown in Fig. 2 (F).
As shown by the solid line, the write pulse W becomes high level.
E1 is supplied to the memory circuit 1.

As a result, the memory circuit 1 writes the pixel data from the latch 3 to the previously designated 16-bit write address as described above during the high level period of the write pulse WE1. Here, the two pixel data are i14.1 kHz
In the case of reproduction with 2, on average, 6 pixel data will be transmitted in 1H period. These six pixel data are written into the memory circuit 1 during the horizontal blanking period (27K).

Next, to explain the readout operation of pixel data of the memory circuit 1, the controller 2 outputs a readout address signal from its terminal 2R, and the second pixel data from its terminals 2c and 2d.
While generating and outputting the pulses shown in Figures (E) and (D),
Pulses RAS shown in FIGS. 2(B) and 2(C) are generated from the terminals 2e and 2f.

Output CAS and connect from terminal 2g to Figure 2 (F)
As shown by the broken line, a low level signal is always output. As a result, after the lower 8 bits and upper 8 bits of the read address signal are sequentially taken into the memory circuit 1, the accumulated pixel data at the read address is read out. Here, as described above, the memory circuit 1 stores a total of six pixel data, one each of four luminance pixel data and two types of color difference pixel data, at the same address.
During the above reading, these six pixel data are read out at once. Among these, the four luminance pixel data are once latched in parallel by the latch driver in the memory circuit 1, and then sequentially taken out in a time-sharing manner within one period of 2.25M)12 latch pulses to the memory group 6a and The signals are respectively supplied to the switch circuits 7a. Further, each one of the two types of color difference pixel data is taken out once within one period of the 2.25MH2 latch pulse, and one color difference pixel data is supplied to the memory group 6b and the switch circuit 7b, respectively,
At the same time, the other color difference pixel data is stored in memory group 6C.
and the switch circuit 7C. Memory group 5a
, 5b and 6C will be described later.

Part or all of the memory circuit 1 serving as the image memory described above is shared as a buffer memory of a computer. The main parts of the computer consist of a central processing unit (CPU) 8 and a keyboard 9, as shown in FIG. C.P.L.J.
8 is generated by the controller 2 in FIG. 3(A), (
A control pulse as shown in B) is supplied to the input port 8a, and the memory circuit 1 is made accessible only during the high level period of the control pulse, and access is prohibited during the low level period of the control pulse. When this control pulse is illustrated at a horizontal scanning period (T1) rate, it becomes as shown in FIG. Corresponds to the erasure period. FIG. 3(B) is a waveform diagram showing the control pulses at a vertical scanning period (V) rate, in which the vertical blanking period (V, BLK) is at a high level, and the other 1V period is at a high level. As shown in Figure (A), the signal is at a high level only during the video period, and is at a low level during the horizontal blanking period, which is indicated by an X mark. Therefore, the CPU 8 can access the memory circuit 1 only during the video period, the vertical blanking period, and a plurality of predetermined fixed periods to be described later.

Within the memory accessible period of the CPU 8,
The CPU 8 supplies a 16-bit address signal to the address latch 10 from its output port 8b, and also supplies a latch pulse to the address latch 10 from its output port 8C. Of the 16-bit address signal (for writing or reading) taken out from the address latch 10, its upper 8 bits are supplied to the driver 11U, and its lower 8 bits are supplied to the driver 11L. Drivers 11U and 11L each have controller 2 only when accessing memory.
Pulses as shown in FIGS. 2(E) and 2(D) are applied from terminals 2h and 21, respectively, and drive control is performed during the low level period of the pulses. Therefore, when the CPLJ8 accesses the memory, the drivers 11L and 11U are sequentially driven, and similarly to the above, the driver 11L is connected to the address terminal of the memory circuit 1 via the common address bus.

Starting from 11U, the lower 8 bits and upper 8 bits of the address signal are
bit is applied.

Furthermore, when the CPU 8 accesses the memory, the CPU 8 generates and outputs pulses as shown in FIG. 2 (G), FIG. .

This pulse is a pulse (referred to as a request pulse) that requests access to the memory circuit 1 at a high level, and when the input pulse of the terminal 2j becomes a high level, the controller 2 outputs the terminals 2a and 2b.
, 2c, and 2d, outputting a higher level signal, and
Pulses shown in FIG. 2 (D) and (E) are generated and output from the terminals 2i and 2h, and a high-level write pulse WE2 as shown by the solid line in FIG. 2 (H) is sent from the output port 8e of the CPU 8 to the terminal 2k. When there is an input, a write pulse WEI is generated and outputted from the terminal 20 at the timing shown by the solid line in FIG. 2(F).

On the other hand, when the input signal to the terminal 2 is at a low level as shown by the broken line in FIG. 2(H), the controller 2 always outputs a low level signal from its terminal 2g.

Here, as shown in FIG. 4(A), the request pulse is at a low level during the 27th horizontal blanking period, and the other periods are marked with an X in FIG. 4(A) and (8), respectively. As shown, it is undefined and becomes high level only when memory is accessed.

Therefore, the request pulse becomes high level, and
When a high-level signal is output from the output port 8e, the memory circuit 1 writes the data applied to the data input terminal from the output port 8f of the CPLI 8 through the latch 12 to the address taken out from the drivers 11U and 11L. Inject. Furthermore, when the request pulse is at a high level and a low level signal is output from the output port 8e, the memory circuit 1 reads the accumulated data at the address taken out from the drivers 11U and 11L, and transfers it to the controller 2°. The latch pulse is applied to the input port 8g of the CPU 8 through the latch 13 to which it is supplied. The CPU 8 processes this input data for graphics and the like.

Here, when the CPU 8 is accessing the memory circuit 1, the pixel data cannot be read out from the memory circuit 1, and dropout occurs as described above, but in this embodiment, this is and 6C, switch circuits 7a, 7b, and 7C, and controller 2. Since the memory groups 6a, 6b, and 6c each have the same configuration, we will explain one memory group 6a among them, and explain the configurations of the other two memory groups 6b and 6c.

A description of the operation will be omitted. One embodiment of the memory group 6a and the switch circuit 7a is as shown in FIG.

In the figure, pixel data from the memory circuit 1 that has entered the input terminal 20 is supplied in parallel to n digital memories 231 to 23n constituting the memory group 6a, and is also supplied to the switch circuit 7a.

The digital memories 231 to 23n each receive pixel data read out from the memory circuit 1 and input via the input terminal 20 (the input pixel data of the memory group 6a is the luminance pixel data described above) during a predetermined period (for example, IH). (456 data in total if the fixed period is 1H) from terminal 211 to
Data is written based on the output control pulse of the controller 2 that constitutes the memory control means supplied via the 2In, but each of the digital memories 231 to 23n has a certain period of time at different positions in the same field (one vertical scanning period). pixel data is written. Therefore, for example, if 0 is set to 23, then the top 10 of the same field are
th, 20th, 30th.

..., 22020th If it is assumed that every 10th scanning line is defined as one day, the pixel data that successively enters the input terminal 20 is the pixel data of the 10th scanning line (10th H or 233rd H). When , the write pulse is applied only to the digital memory 231 and the write pulse is applied only to the digital memory 231.
written only to Similarly, digital memory 2
32.23a,...

23n has the 20th, 30th, etc., 2202
Pixel data of the 0th scan line is written respectively.

When the above write operation is completed in one vertical scanning period, the CPLJ 8 accesses the memory circuit 1 during one or more of the predetermined fixed periods in the next vertical scanning period. .

That is, the CPU 8 can access the memory circuit 1 in each of the plurality of predetermined periods at maximum.

On the other hand, the switch circuit 7a shown in FIG. 5 constitutes the above-mentioned switch circuit means together with the switch circuits 7b and 7c shown in FIG. The pixel data is passed through and output as is to the output terminal 24, but when writing/reading is performed in the memory circuit 1 of the CPIJ8, the pixel data from one vertical scanning period before the certain period in which the access was performed is stored and processed. The input terminal 22 is controlled by the controller 2 to selectively output the output pixel data of the digital memory 231 (where i is any one of 1 to n).
The switching is controlled by a switching pulse applied through the .

At the same time, the stored pixel data of the digital memory 23i is read out by a control pulse applied from the controller 2 via the input terminal 21i. The pixel data for a certain period read from the digital memory 23i passes through the switch circuit 7a and is output to the output terminal 24 as output pixel data. Figure 6 (A), (
B) and (C) are input terminals 21 from the controller 2, respectively.
t.

An example of a control pulse waveform input to 212 and 213 is shown. In the first vertical scanning period (1v), a write operation is performed during the high level period, and from the next vertical scanning period onwards, a read operation is performed during the high level period, but as described above, during the high level period, the CPU 8 This occurs depending on the period during which the memory circuit 1 is accessed.

Note that the pixel data written in the digital memories 231 to 23n is updated by updating the pixel data taken out from the memory circuit 1 during the corresponding fixed period when the CPU 8 does not access it during the corresponding fixed period. This is done by writing it into digital memory. Alternatively, writing may be performed while sequentially adding addresses of pixel data stored in the digital memories 23+ to 23n at a constant or arbitrary value. That is, in this case, a plurality of fixed periods predetermined in each of the digital memories 23+ to 23n are sequentially changed for each vertical scanning period, and pixels read out from the memory circuit 1 in each changed fixed period are Write the data to the corresponding one digital memory.

Returning to FIG. 1 again, the luminance pixel data thus extracted from the switch circuit 7a and the two types of color difference pixel data extracted from the switch circuits 7b and 7c are respectively supplied to the DA converter 14. , where they are separately converted into analog signals and then supplied to the encoder 15. The encoder 15 generates a composite video signal to which horizontal and vertical synchronization signals and color burst signals are added and complies with a predetermined standard method, and replaces the video information with a signal from the character generator 16 as necessary. After that, it is output to the monitor device via the output terminal 17. In this way, even when accessing memory by CPU,
Good images without noise can be reproduced.

Note that the present invention is not limited to the above-described embodiments; for example, pixel data input manually to the memory circuit 1 may be input to pixel data input via a recording medium other than a digital audio disk or via another transmission path. can also be applied. Furthermore, the memory capacity of the digital memories 231 to 23n is not limited to 1H, and may be smaller or larger than that.

Effects of the Invention As described above, according to the present invention, even if the image memory, part or all of which is shared as a buffer memory for a computer, is accessed during the read period, dropouts will not occur in the reproduced composite video signal. Therefore, it is possible to obtain a good playback image without noise, and it also ensures substantially high calculation speed for still images or slow-moving videos, and it is possible to obtain a good playback image without affecting the playback image at all. It has many features such as being able to obtain a reproduced image and increasing the speed of change in graphics that can be expressed by a central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the device of the present invention;
Figures 2, 3 and 4 are signal waveform diagrams for explaining the operation of the block system shown in Figure 1, respectively, and Figure 5 is a block system diagram that does not show the main components of the block system shown in Figure 1. , FIG. 6 is a signal waveform diagram for explaining the operation of the block system shown in FIG. DESCRIPTION OF SYMBOLS 1...Memory circuit, 2...Controller, 5a. 5b, 5c =--memory group, 7a, 7b,
7c - Switch circuit, 8 Central processing unit (
CPU), 20... Pixel data input terminal, 211-2
1n...Control signal input terminal, 22...Switching signal input terminal, 231-23n...Digital memory. Fig. 2 11 141, IH-, 1 Fig. 4 + + V - 121 Fig. 5 6Q → Kicho Town

Claims (3)

[Claims] (1) A device that writes input pixel data within the horizontal blanking period of the final output composite video signal and reads out the written pixel data during the video period. Part or all of the image memory is shared as a buffer memory for the central processing unit. , a plurality of digital memories respectively storing pixel data read out from the image memory in a plurality of predetermined fixed periods different from each other within one vertical scanning period; The output pixel data of the image memory for the certain period is written into the corresponding digital memory, and when the image memory is accessed by the central processing unit, at least one vertical scanning period before the access period among the plurality of digital memories. a memory control means for reading out pixel data from one digital memory storing pixel data for the certain period of time; and the central processing that is performed during any one or more certain periods of the plurality of certain periods. A switch circuit that selectively outputs the output pixel data of the one digital memory read by the memory control means when the image memory is accessed by the apparatus, and allows the output pixel data of the image memory to pass through and output as is when there is no access. A correction device for an image memory, comprising: means. (2) The memory control means, during a certain period of time when the image memory is not accessed by the central processing unit among the plurality of certain periods, transfers the pixel data read from the image memory during the certain period to the corresponding one. 2. The image memory correction device according to claim 1, wherein the image memory correction device writes data into a digital memory. (3) The memory control means sequentially changes the plurality of fixed periods predetermined in each of the plurality of digital memories for each vertical scanning period, and controls the image memory during the changed fixed period. 2. The image memory correction device according to claim 1, wherein the pixel data read out from the pixel data is written into a corresponding digital memory.