GB2249415A - Addressing frame data in memory - Google Patents

Addressing frame data in memory Download PDF

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Publication number
GB2249415A
GB2249415A GB9117389A GB9117389A GB2249415A GB 2249415 A GB2249415 A GB 2249415A GB 9117389 A GB9117389 A GB 9117389A GB 9117389 A GB9117389 A GB 9117389A GB 2249415 A GB2249415 A GB 2249415A
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United Kingdom
Prior art keywords
memory
data
signals
frame
addressing
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9117389A
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GB9117389D0 (en
Inventor
Yong-Je Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9117389D0 publication Critical patent/GB9117389D0/en
Publication of GB2249415A publication Critical patent/GB2249415A/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Signal Processing For Recording (AREA)
  • Dram (AREA)

Abstract

An addressing method for addressing frame data in a memory in a video recording and/or reproducing apparatus using a low-priced DRAM memory instead of a high-priced SRAM or field memory. The method comprises the steps of dividing a DRAM memory into sub-memory regions which are successively addressed at a rate which avoids the need for separate refreshing. <IMAGE>

Description

2 24 914 1 j ADDRESSING FRAME DATA IN MEMORY The present invention relates
to the addressing of frame data in a memory used for storing and reading out the frame data in a video recording 5 and/or reproducing apparatus.
Generally, one frame data is delayed by a delay device so as to separate a motion signal and a colour signal from a composite video signal when a video signal is recorded on and reproduced from a magnetic tape in a video recording and/or reproducing apparatus. A memory device is usually used as the delay device. That is, as shown in Figure 1 of the accompanying diagrammatic drawings, which depicts a block diagram of a part of a video recording and/or reproducing system to which embodiments of the present invention may be applied, an analogue composite video signal fed into A/D converter 10 is converted into a digital composite video signal, then timebase-aligned regularly in time-base -correction portion 20 (hereinafter, referred to as TBQ, and then frame-combed in frame comb portion 50. The frame comb portion 50, consisting of memory device portion 30 and adder 40, frame-combs the time-base-corrected signal supplied from TBC 20, and transmits the frame-combed signal to a motion and colour signal separator. The memory device portion 30 includes a memory device and a control circuit (not shown) for controlling the writing-in and reading-out operations of the frame data in the memory device. A memory device such as SRAM, field memory or DRAM can be used in a video recording and/or reproducing system to which embodiments of the present invention may be applied.
When a memory device such as SRAM or field memory is used, unlike using a DRAM, a separate refresh control circuit is not required, but a disadvantage is that the device tends to be expensive. Then, when using a DRAM as a memory device, the time required for storing one data frame therein may take 512 x 63.5ps = 30ms for a 2 megabyte memory in the case of addressing the image data of every horizontal synchronous signal period 1H, row by row, to the DRAM memory whenever each row address strobe signal RAS is supplied therein, as illustrated in Figure 3A of the accompanying diagrammatic drawings. Therefore, when storing one frame data into a DRAM memory, it is impossible to meet a refresh cycle of the DRAM memory, which should be usually refreshed every 4 to 8ms, without using a refresh control circuit. For this reason, even though the price of the DRAM memory device is low, the cost of the entire apparatus due to its complicated constitution is increased when using a DRAM.
Therefore, preferred embodiments of the present invention aim to provide an addressing method for writing in or reading out one frame data in or from a DRAM without a sep&ate refresh control circuit when using a DRAM as a memory device used in a video recording and/or reproducing apparatus.
According to a first aspect of the present invention, there is provided an addressing method for a DRAM memory for use in writing in or reading out one frame image data in accordance with row address strobe signals (RAS), column address strobe signals (CAS), and address signals (ADDR) determined by both of the above strobe signals, which are supplied as memory control signals, said method comprising the steps of:
1 supplying m row address strobe signals, n column address signals, and the corresponding m - n address signals in sequence to said DRAM memory for the period of one horizontal synchronous signal; writing or reading out data having rn x n x (number of sampling bits) sequentially in or from a sub-memory region having said mX n addresses for the period of one horizontal synchronous signal period by supplying said n column address strobe signals and said corresponding n address signals sequentially to said DRAM memory whenever each of said rn row address 10 strobe signals is input to said DRAM memory; supplying next n column address strobe signals whenever each of said row address strobe signals is input when said writing in and reading out operations are completed by supplying all the row address strobe signals in said DRAM memory to said n column address strobe signals, and repeating the above entire steps until one frame image data is entirely written or read out in or from said DRAM memory.
Said memory may be composed of 512 row address sections and 512 column address sections, and has a capacity of 2 megabytes (= 512 x 512 x 8 bits) when the number of sampling bits is eight.
m may equal 16 and n may equal 32.
Said sub-memory region may be composed of 16 row address sections and 32 column address sections.
According to a second aspect of the present invention, there is provided an addressing circuit for frame data in a memory adapted to write or read out one frame data in or from a video recording and/or reproducing apparatus, comprising:
memory means for storing data to write in or read out a predetermined number of data of said one frame data; timing control means for supplying timing control signals to said memory means; and a data selector for selecting the predetermined data written in or read out from said memory means according to control signals of said timing control means, and supplying the selected data to an adder.
Preferably, said memory means consistsof first and second frame data memories, each having a predetermined capacity.
Preferably, said first and- second frame memories are constituted in such a manner that one performs a writing operation, while the other performs a reading operation.
Preferably, each of said first and second frame memories has 512 x 512 x 8 bits, that is, a capacity of 2 megabytes.
According to another aspect of the present invention, there is provided a method of or circuit for addressing frame data in a memory, wherein a DRAM memory is sub-divided into sub-memory regions which are successively addressed at a rate which avoids refreshing of the memory.
Such a method or may further comprise any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.
The invention also extends to a video recording and/or reproducing apparatus adapted to operate in accordance with a method, or incorporating 10 a circuit, according to any of the preceding aspects of the invention.
For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 2 to 3B of the accompanying diagrammatic drawings, in which:
Figure 2 is a block diagrani schematically showing one example of a circuit for writing or reading out a frame data in or from a memory embodying the present invention; and Figures 3A and 3B illustrate in detail examples of memory layouts for explaining the addressing methods of a frame data within a memory according to a conventional method and an embodiment of the present invention, respectively.
The capacity of a memory for writing in and reading out one frame of data in a video recording and/or reproducing system ordinarily requires more than 2 megabytes (512 x 512 x 8 bits). Referring to Figure 2, here, two memories of 2 megabytes are used in the present embodiment, whereby when one memory performs a writing-in operation, the other is made to perform a reading-out operation.
Though the writing-in and reading-out operations will be explained with two memories used in the present embodiment, it should be noted that the present invention is not limited thereto, and it is possible to use a single memory having a suitable capacity.
As shown in Figure 2, a digital composite video signal time-basecorrected in TBC 20 is supplied to adder 40 and data selector 34. The video signals output from TBC 20, that is, the digital data, are written in or read out from first or second frame memory 31 or 32 through data selector 34. That is, data selector 34 writes the digital data in first or second frame memory 31 or 32 or reads out the written data therefrom, so as to supply the read-out data to adder 40 according to memory control signals output from timing block 33. The write enable and read enable signals W-E and OE from timing block 33 are operated in an active low state. Thus, when a high signal is generated from timing block 33, read enable signal OE is enabled in the first frame memory 3 1, and write enable signal WE is enabled in the second frame memory 32. Meanwhile, if a low signal is generated from timing block 33, the WE signal is enabled in the first frame memory 31, and OE signal is enabled in the second frame memory 32. In other words, while first frame memory 31 performs the write-in operation, second frame memory 32 the read-out operation, and data selector 34 writes in or reads out the data from the first and second frame of memory 31 and 32. At this time, timing block 33 supplies row address strobe signal RAS, column address strobe signal CAS and address signal ADDR to first and second frame memory 31 and 32, thereby accessing addresses in a memory.
1 Now, an example of a frame data addressing method in a memory such as that illustrated in Figure 2 will be described, referring to Figures 3A and 3B.
As shown in Figure 3A, which illustrates a conventional method, so far, the frame data has been stored row by row into a memory in order to write the frame data therein. That is, whenever every RAS signal is received, the frame data is written in the memory row by row during the IH period. Here, the unit H is 63.5/is, that is, 1/fH in which fH is a frequency of a horizontal synchronous signal, that is fH = 15.734 KHz in the NTSC television system (for example). Thus, as described above, the time to write one frame of data takes a total of about 30ms in the case of a 512 x 512 DRAM memory device - that is, of a size as employed in the embodiment of Figure 2. Accordingly, the DRAM memory device having an ordinary refresh cycle of 4 to 8ms also requires an extra refresh control circuit for refreshing the DRAM memory pefiodically.
However, to use a low-priced DRAM memory device without a refresh control circuit when writing in and reading out one frame data from the memory adapted in a video recording and/or reproducing apparatus, a method embodying the present invention divides the DRAM memory into a plurality of sub-memory regions, and writes in and reads out a predetermined number of data from the divided sub-memory regions for every horizontal synchronous signal period. That is, whenever each of the row address strobe signals RAS is input to the memories 31 and 32, n column address strobe signals CAS and the corresponding n address signals ADDR are sequentially input to the memories 31 and 32. Thus, when m row address strobe signals RAS are input to the memories 31 and 32 for one horizontal synchronous signal period, data having a predetermined number of bits, that is m x n x (sampling bits) are written in or read out from the sub-memory regions. Then, when the writing and reading operations are completed by supplying all the row address strobe signals RAS depending on the n column address strobe signals CAS, the next n column address strobe signals CAS are supplied to the sub-memory regions whenever each of the row address strobe signals RAS is supplied thereto. And then, the above writing and reading operations are repeated until one frame of image data is completely written in or read out from the divided sub-memory regions.
To illustrate this, with reference to Figure 3B, the 512 x 512 DRAM memory device of the circuit of Figure 2 is divided into 512 sub-memory regions each of which has 16 row addresses and 32 column addresses.
Therefore, a frame data of 4096 (16 x 32 x 8) bits are written in or read out in accordance with row address strobe signal RAS, column address strobe signal CAS address signal ADDR; write enable signal WE and read enable signal OE generated from timing block 33 of Figure 2 during a horizontal synchronous signal period 1H from a sub-memory region.
That is, whenever one row address strobe signal RAS is input to the memory, the column address strobe signals CAS of the 0 through 31 column address sections are sequentially supplied thereto. Accordingly, as row address strobe signals RAS of the 0 through 15 row address sections are sequentially supplied to the memory for one horizontal synchronous signal period, a total of 4096 bits of data are written in or read out from the sub memory regions defined by both the strobe signals and the corresponding address signals. Then, row address strobe signals of row address section 16 through 31 are sequentially supplied to the memory for another horizontal synchronous signal period, and simultaneously, the column address strobe signals of the 0 through 31 column address section and the corresponding address signals are sequentially supplied to the memory. Accordingly, the next 4096 bits of data are written in or read out from another sub-memory region defined by the row address strobe signals of the 16 through 31 row address section, the column address strobe signals of the 0 through 31 column address section and the corresponding address signals. Sequentially, when the data are completely written in all row address sub- memory regions belonging to the 0 through 31 column address section, that is, the 0 through 511 row address section in the present embodiment, other data are written in row address sub-memory regions belonging to the 32 through 63 column address section.
The operation repeats until the one frame data is completely written in or read out from the entire sub-memory regions of a 512 x 512 memory device. In a 512 x 512 DRAM niemory adapted to this embodiment of the present invention, 16 row address strobe signals are supplied to the memory for the duration of one horizontal synchronous signal period. Accordingly, 512 (= 16 x 32) row address strobe signals are supplied to the entire memory for a 32 horizontal synchronous signal period. Thus, it takes about 2.4 ms (= 32 x 63.51ts) to supply the row address strobe signals of the 0 through 511 row address sections for each 32 horizontal synchronous signal period. Therefore, each of the sub-memory regions in the DRAM memory does not require to be refreshed at a certain period because the row address strobe signals of 0 through 511 row address section are sequentially supplied to the memory within the refresh cycle of the DRAM memory, that is, at a 32 horizontal synchronous signal period.
is In short, an addressing method for a frame of data in a DRAM memory used in a video recording and/or reproducing apparatus in an embodiment of the present invention, using a DRAM memory and not an expensive SRAM or a field memory, requires no extra refresh control circuit in writing in or reading out one frame data from a low-priced DRAM memory obtaining, as a result, a more simplified design.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combind in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (14)

  1. W 1. An addressing method for a DRAM memory for use in writing in or reading out one frame image data in accordance with row address strobe signals (RAS), column address strobe signals (CAS), and address signals (ADDR) determined by both of the above strobe signals, which are supplied as memory control signals, said method comprising the steps of:
    supplying m row address strobe signals, n column address signals, and the corresponding m - n address signals in sequence to said DRAM memory for the period of one horizontal synchronous signal; writing or reading out data having m x n x (number of sampling bits) sequentially in or from a sub-memory region having said mX n addresses for the period of one horizontal synchronous signal period by supplying said n column address strobe signals and said corresponding n address signals sequentially to said DRAM memory whenever each of said m row address strobe signals is input to said DRAM memory; supplying next n column address strobe signals whenever each of said row address strobe signals is input when said writing in and reading out operations are completed by supplying all the row address strobe signals in said DRAM memory to said n column address strobe signals; and repeating the above entire steps until one frame image data is entirely written or read out in or from said DRAM memory.
  2. 2 2. An addressing method as claimed in Claim 1, wherein said memory is composed of 512 row address sections and 512 column address sections, and has a capacity of 2 megabytes (= 512 x 512 x 8 bits) when the number of sampling bits is eight.
  3. 3. An addressing method as claimed in Claim 2, wherein m is equal to 16 and n is equal to 32.
  4. 4. An addressing method as claimed in Claim 3, wherein said sub-memory region is composed of 16 row address sections and 32 column address sections.
  5. 5. An addressing circuit for frame data in a memory adapted to write or read out one frame data in or from a video recording and/or reproducing apparatus, comprising:
    memory means for storing data to write in or read out a predetermined number of data of said one frame data; timing control means for supplying timing control signals to said memory means; and a data selector for selecting the predetermined data written in or read out from said memory means according to control signals of said timing 25 control means, and supplying the selected data to an adder.
  6. 6. An addressing circuit as claimed in Claim 5, wherein said memory means consists of first and second frame data memories, each having a predetermined capacity.
  7. 7. An addressing circuit as claimed in Claim 6. wherein said first and second frame memories are constituted in such a manner that one performs a writing operation, while the other performs a reading operation.
  8. 8. An addressing circuit as claimed in Claim 6 or 7, further comprising an inverter installed in an output line of said timing control means in order that said first and second frame memories are operated in an active low state. after receiving a signal supplied from said timing control means.
  9. 9. An addressing circuit of frame data as claimed in Claim 6, 7 or 8, wherein each of said first and second frame memories has 512 x 512 x 8 bits, that is, a capacity of 2 megabytes:
  10. 10. An addressing circuit for frame data, substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.
  11. 11. An addressing method for frame data, substantially as hereinbefore described with reference to Figure 3B of the accompanying drawings.
  12. 12. A method of or circuit for addressing frame data in a memory, wherein a DRAM memory is sub-divided into sub-memory regions which are successively addressed at a rate which avoids refreshing of the memory.
  13. 13. A method or circuit according to claim 12, further comprising any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.
  14. 14. A video recording and/or reproducing apparatus adapted to operate in accordance with a method, or incorporating a circuit, according to any of the preceding claims.
GB9117389A 1990-10-31 1991-08-12 Addressing frame data in memory Withdrawn GB2249415A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900017581A KR920009770B1 (en) 1990-10-31 1990-10-31 Frame data addresing method for vtr

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Publication Number Publication Date
GB9117389D0 GB9117389D0 (en) 1991-09-25
GB2249415A true GB2249415A (en) 1992-05-06

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JP (1) JPH06325566A (en)
KR (1) KR920009770B1 (en)
DE (1) DE4127280A1 (en)
GB (1) GB2249415A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2267590B (en) * 1992-05-29 1996-03-27 Gold Star Co Memory access delay control circuit for image motion compensation
KR970008412B1 (en) * 1993-10-15 1997-05-23 엘지반도체 주식회사 Memory system for digital image signal processing
DE19940923A1 (en) * 1999-08-27 2001-03-08 Forschungszentrum Juelich Gmbh Read/write method for storing/extracting signal pattern using dynamic semiconductor store with data stored in form of matrix refresh each line with each read/write operation
JP4964091B2 (en) * 2007-10-30 2012-06-27 川崎マイクロエレクトロニクス株式会社 MEMORY ACCESS METHOD AND MEMORY CONTROL DEVICE

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137377A (en) * 1982-02-09 1983-08-15 Victor Co Of Japan Ltd Digital video signal transmitter
US4587559A (en) * 1983-03-11 1986-05-06 Welch Allyn, Inc. Refreshing of dynamic memory
EP0249985B1 (en) * 1986-06-20 1993-09-08 Sony Corporation Video memory
DE3913599C1 (en) * 1989-04-25 1990-01-18 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung Ev, 8000 Muenchen, De Intermediate image store e.g. for TV transmission - assigns separate control to each video channel for connection to all memory blocks

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Publication number Publication date
DE4127280C2 (en) 1993-01-07
JPH06325566A (en) 1994-11-25
DE4127280A1 (en) 1992-05-14
KR920009770B1 (en) 1992-10-22
KR920008672A (en) 1992-05-28
GB9117389D0 (en) 1991-09-25

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