JPH04114195A - Image storing device - Google Patents

Abstract

PURPOSE:To miniaturize a device and to reduce the cost of the device by provid ing a 1st field memory having an n0 bit constitution (n0<N) and a 2nd field memory having an n1 bit constitution (n1<N) with reference to a digital video signal with N bits. CONSTITUTION:The digital video signal with N bits is processed by the 1st and 2nd field memories 24 and 26 having the n0 and n1 bit constitution. In the case of storing two images, the gradation of the video signal of a 1st image is decreased to a prescribed n0 bit per one dot so as to write in the 1st field memory 24, and the gradation of the video signal of the 2nd image is decreased to a prescribed n1 bit per one dot so as to write in the 2nd field memory 26 by a system controlling gate array 20. Then, two images stored in the 1st and 2nd field memories 24 and 26 can be separately read out and separately displayed or recorded, and they can be displayed or recorded as one synthesized picture by selectively reading them within one field cycle. Thus, the picture synthesis can be performed by a small storing capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image storage device used in a video printer or the like.

[Prior Art] An image recording device such as a video printer takes in video signals from a television receiver, VTR, etc., stores them in an image memory, and then reads out the video signals from the memory and displays them on a display screen. or print it out on paper.

A digital video signal input to such a recording device is quantized on a pixel (bit) basis, and the number of gradations of a pixel is determined by the number of quantizations. For example, an 8-bit digital video signal can express 256 (28) levels of gradation.

[Problems to be Solved by the Invention] Conventionally, an input N-bit digital video signal has been stored in a field memory having an N-bit configuration. Therefore, when performing screen composition, two N-bit field memories are provided as means for respectively storing two images to be composited. However, field memory is an expensive component, and doubling this storage capacity would result in a considerable increase in cost, which would be a drawback for popular devices.

The present invention has been made in view of such problems, and an object of the present invention is to provide an image storage device that can perform screen composition with a small storage capacity.

[Means for Solving the Problems] In order to achieve the above object, the first image storage device of the present invention stores a digital video signal of N bits per dot before displaying it on a screen or recording it on paper. An image storage device for once storing the digital video signal includes a first field memory having an nO bit configuration (nO<N), a second field memory having an nl bit configuration (nl<N), and a second field memory having an nl bit configuration (nl<N). The present invention is configured to include means for writing only no focus per dot into the first field memory and writing the digital video signal by n1 bits per dot into the second field memory.

Further, the second image storage device of the present invention is a 1-domain image storage device.

an image storage device for temporarily storing a digital video signal of N bits per field prior to displaying it on a screen or recording it on paper; first and second field memories each having an N/2 bit configuration; Means for writing the digital video signal by N/2 upper or lower bits per dot into a first field memory, and writing the digital video signal by N/2 upper or lower bits per dot into a second field memory. The configuration includes the following.

[Operation] The first image storage device is the basic device of the present invention,
The first .nLnl bit configuration (no, nl <N). The second field memory processes N-bit digital video signals.

When storing one image, the first and second field memories are connected and used as a (nO+nl) bit field memory. If N≧(nO+nl) for each N-bit data of the video signal, the upper (nO+
nl) bits are written to the field memory of (nO+n1) bits, and if N<(nO+nl), they are written to the pair field memory left-justified or right-justified, and O is substituted for the remaining focus. When outputting this image, (
n.

+ n I) Read from the bit field memory.

That is, n O+n 1 bits of data read from the first and second field memories are combined to restore (nO+nl) via).

When storing two images, the video signal of the first image is written to the first field memory with the gradation reduced to a predetermined nO bit and 7 dots per dot, and the video signal of the second image is written to the first field memory. The gradation is reduced to a predetermined nl bits per dot and written to the second field memory. For the two images thus stored in the first and second field memories, they can be read out separately and displayed or recorded separately, or they can be selectively displayed within one field period. It is also possible to display or record it as one composite screen by reading it out.

Thus, according to the first device, no bit configuration (n
O<N) field memory and nl bi.

By using a field memory with an N-bit configuration (nl <N), it is possible to obtain functions (such as one-screen playback and two-screen compositing) that are equivalent to when using two field memories with an N-bit configuration. Furthermore, when performing two-screen composition, the upper nO bits of the first image data are stored in the first memory, the upper nl bits of the second image data are stored in the second memory, and then the upper nl bits of the second image data are stored in the second memory. The data of nO and nl bits read from the first and second field memories are combined to form (nO+n
1) 2r by displaying or recording as bits
It is also possible to realize a composite screen of a second screen with a gradation representation of 211 steps with a stiffness contrast ratio of approximately 2 rLo times on a first screen with a 10-step gradation representation.

The second image storage device is a case in which both field memories in the first device are each configured with N/2 bits. When storing one image, the upper N/2 bits of each N bit of the input video signal are written to, for example, a first field memory, and the lower N/2 bits are written to a second field memory. When storing two images, the video signal of the first image is written to the first field memory with the gradation lowered to the upper N/2 bits or the lower N/2 bits, and the second image is stored in the first field memory. The signal is written to the second field memory with the gradation reduced to upper N/2 bits or lower N/2 bits. The two images stored in the first and second field memories in this way can be displayed or recorded separately as two screens with 2N/L gradation representation, or can be displayed or recorded in one frame. It is also possible to display or record them as one composite screen with gradation expression in 2NIL stages by selectively reading them within the pulse cycle.

According to this second device, the two field memories each having an N-bit configuration can provide the same function as when two field memories each having an N-bit configuration are provided.

When performing two-screen compositing, the upper N/
After storing 2 bits in the first memory and storing the upper N/2 bits of the second image data in the second memory, the first
By combining the data read from the second field memory and displaying or recording it as N bits, a contrast ratio of approximately 21V/2 times is displayed on the first screen with 2N/z step gradation expression. Small 2 N/z
It is also possible to realize a composite screen of the second screen with stepwise gradation representation.

[Embodiment 1] In the embodiment according to claim (2) of the present invention, one dot is an 8 (N) bit digital video signal, and 4 (
1 shows an example of a configuration of a main part of an image storage device including first and second field memories having an N/2) bit configuration.

This device is installed in a video printer, for example, and performs the processing of capturing a video signal from a video source such as a television receiver, storing it in memory, and then reading the video signal from memory and sending it to a display circuit or printed circuit. This image storage function makes it possible to display or record a still image 9 composite screen, etc. This device has a first mode in which one image is stored and read out, a second mode in which two images are stored and selectively read out, and a second mode in which two images are stored and successive data is combined into HO+nl) bit data. There is a third mode.

In this device, an analog video signal input to an input terminal 10 is converted into an 8-bit digital video signal by an A/D converter 14 at a sampling frequency corresponding to the pixel density, and this digital video signal is sent to a system control gate array. 20 is input. On the other hand, horizontal and vertical synchronizing signals are input to the CPU 18 from the input terminal 12, and the CPU
A write address signal of the digital video signal is supplied from olB to the gate array 20 via the address conversion ROM 18.

The gate array 20 is connected to address terminals of field memories 24 and 26, each of which has a 4-bit configuration, via a 16-bit notress bus 32, and an 8-bit data bus 34. ．． Selector 2
It is connected to the data terminals of these memories via 2 and 4 bit data buses 36 and 38.

The gate array 20 and selector 22 perform the following control for each mode on both field memories 4 and 26 under the control of the CPU 16.

(A) First mode When writing a video signal to the field memory in this mode, the gate array 20 is connected to both field memories 24 and 26.
Write control signals WHO and WEI are simultaneously applied to the dots, a write address signal is outputted onto the address bus 32 for each dot, and an 8-bit digital video signal is outputted onto the data bus 34. The selector 22 simultaneously distributes the upper 4 bits of each 8-bit data (video signal) inputted from the gate array 20 to the field memory 24 and the lower 4 bits to the memory 26. As a result, the digital video signal for one screen is stored in both field memories 24 and 28 with the same 8-bit information as when it was input.

When reading a video signal for screen display or printout, a read address signal is applied from the CPU 16 to the gate array 20 via the address conversion ROM 18. Gate array 20 outputs a read address signal onto address bus 32 while simultaneously applying read control signals OEO and OEt to both field memos U24 and U26, respectively. This memory access allows both field memories 24.2
The 4-bit digital video signals read from 6 are combined by the selector 22 into 8 vias 1-. As a result, the same 8-bit digital video signal as before writing is taken into the gate array 20. This digital video signal is converted into an analog video signal by the D/A converter 28, and then sent from the output terminal 30 to a display circuit or the like.

In this way, in the first mode, both field memories 24
．． 26 cooperate to form a memory equivalent to a normal 8-bit field memory, and output the input 8-bit digital video signal with the same amount of information. Therefore, 256 levels of gradation expression are possible.

(B) Second mode In the second mode, two images have the same number of bits (N/2
) is stored in the field memory 24.28. First, when a video signal for the first image is input, the gate array 20 applies a write control signal WHO only to the field memory 24 in order to write the video signal into the field memory 24. The selector 22 selects the upper 4 pins of each 8-bit data received from the gate array 2o and outputs them onto the data bus 36. As a result, the digital video signal of the first image is stored in the field memory 24 only for the upper four bits for each dot. Similarly, the digital video signal of the second image is stored in the field memory 28 for only the most significant four bits for each dot.

In this mode, it is possible to display the first and second images separately, or to combine them and display them together.

When outputting the first image in the former case (separate display),
Gate array 20 outputs a read address signal onto address bus 32 while providing successive control signal OEO only to field memory 24 . The selector 22 combines the 4-bit data read out from the field memory 24 with zero data for the lower 4 bits to form 8-bit data.

Thus, an 8-bit digital video signal (the lower 4 bits are zero) is sent to the D/A converter 2 from the gate array 20.
Output to the 8 side. Similarly, the second image is also output as an 8-bit (the lower 4 bits are zero) digital video signal. 18 (24) each
Two screens of gradation can be displayed or recorded separately at any time.

In the latter case (screen composition), the gate array 20 provides readout control signal OEO only to the field memory 24 in the screen area of the first image, and provides readout control signal OEO only to the field memory 26 in the screen area of the second image. An address signal is output onto the address bus 32 while providing a control signal OEI. As a result, in the screen area of the first image, a 4-bit digital video signal corresponding to that screen area is read out from the field memory 24, and in the screen area of the second image, a 4-bit digital video signal corresponding to that screen area is read out from the field memory 26. A 4-bit digital video signal is read out. The selector 22 adds zero data for the lower 4 bits to the 4-bit data taken in from the field memory 24 or 26 to create 8 bits.

It is then sent to the gate array 20. As a result, a 16-gradation screen is obtained by combining the first and second screens.

(C) Third mode In the third mode, like the second mode, only the upper 4 bits of the video signals of the first and second images are written into the field memory 24.243. Then, as in the first mode, the 4-bit digital video signal read from both field memories 24 and 26 is converted to 8 bits by the selector 22.
This digital video signal is coupled to the D/A
The signal is converted into an analog video signal by the converter 28, and then sent out from the output terminal 30 to a display circuit or the like.

In this third mode, the second image data is output in a form shifted by 4 bits to the right of the first image data, and weighted at 1/16. Therefore, on the screen of 16 gradations (4 bits) of the first image signal, the 16th gradation (m) of the second image signal
4 bit) screen is +! The images are combined with a weighting (contrast ratio) of fr 1/18. Such a display with different weighting (contrast ratio) is performed when the main image (first image) of a person etc. and the background image (second image) of scenery etc. are combined using weighting (contrast ratio). suitable for

[Effects of the Invention] By having the above-described configuration, the present invention provides the following effects.

According to the image storage device of claim 1, for an N-bit digital video signal, the first field memory has a no-bit configuration (nO<N) and the first field memory has an n1-bit configuration (nl <N).
By using the second field memory, functions equivalent to those of the conventional memory configuration (2N configuration) (single-screen playback, two-screen composition, etc.) are obtained, making the device smaller and cheaper. I can do it. Also, when performing two-screen compositing,
The upper no focus of the first image data is stored in the first field memory, the upper n1 bits of the second image data are stored in the second field memory, and the data is combined when reading out the nO+nl) bit data. By doing so, it is possible to obtain composite images with different weightings (contrast ratios).

According to the image storage device of claim 2, for an N-bit digital video signal, the first and second field memories each have an N/2 bit configuration, which is half of the conventional memory configuration (2N configuration). Since the same functions (single-screen playback, two-screen composition, etc.) are obtained with the same memory capacity, the device can be made smaller and lower in price. In addition, when performing two-screen composition, for the first image, the upper N/2
The bits are stored in the first field memory, and for the second image, the upper N/2 bits are stored in the second field memory, and the data is combined into N-bit data when successive images are generated. It is possible to obtain composite images with different contrast ratios.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an image storage device according to an embodiment of the present invention. 16...CPU. 20... System control gate array, 22...
Selector, 24.26...Field memory, 28...D
/A converter, 32 song address bus, 34... (8 bits) data bus (8 bits),
36.38... (4 bits, g) data bus.

Claims (2)

[Claims] (1) In an image storage device for temporarily storing a digital video signal of N bits per dot before displaying it on a screen or recording it on paper, the first field memory has an n0 bit configuration (n0<N). and a second field memory having an n1 bit configuration (n1<N); writing the digital video signal by n0 bits per dot into the first field memory, and writing the digital video signal by n1 bits per dot into the first field memory; Second
An image storage device comprising: means for writing into a field memory; (2) In an image storage device for temporarily storing a digital video signal of N bits per dot before displaying it on a screen or recording it on paper, first and second signals each having an N/2 bit configuration are used. a field memory; writing the digital video signal by N/2 upper or lower bits per dot into the first field memory; and writing the digital video signal by N/2 upper or lower bits per dot into the second field memory; An image storage device comprising: means for writing into a field memory;