JPS6130745B2 - - Google Patents
Info
- Publication number
- JPS6130745B2 JPS6130745B2 JP9077378A JP9077378A JPS6130745B2 JP S6130745 B2 JPS6130745 B2 JP S6130745B2 JP 9077378 A JP9077378 A JP 9077378A JP 9077378 A JP9077378 A JP 9077378A JP S6130745 B2 JPS6130745 B2 JP S6130745B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- terminal
- hybrid integrated
- terminal pins
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 238000003780 insertion Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000037431 insertion Effects 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 210000000078 claw Anatomy 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
Landscapes
- Combinations Of Printed Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法に関するもの
で、特に量産性の向上、信頼性の向上を図らんと
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly aims to improve mass productivity and reliability.
従来の半導体装置の製造方法としては、例えば
第1図に示す方法が知られている。この方法は第
1図A〜Dに示すように、先づ複数の回路基板1
に対して夫々例えば半田印刷法あるいは基板デツ
プによるレフロー法等によつて各部品2をマウン
トする。3は配線パターンの端子部である。一方
所定の治具4に予め各回路基板1に対応するよう
に複数の端子ピン5を等間隔に配列したものを用
意する。そして、この状態で各端子ピン5を夫々
の回路基板1の端子部3に半田付けし、その後樹
脂モールドが施される。6は半田である。しか
し、このような方法で作られた混成集積回路は端
子ピン5の熱的強度が弱いという欠点がある。す
なわち、このようにして得た混成集積回路はその
後、プリント基板等のマザーボードに半田付けに
よつてマウントされ所望の半導体装置を得るわけ
であるが、このときの半田熱で混成集積回路内の
端子ピン5と端子部3間の半田が溶け、端子ピン
がずれる等の不都合が生ずる。この欠点を解消す
るためには、例えば混成集積回路における端子ピ
ン5と端子部3の接続に用いる半田として高温半
田を使うことが考えられるが、高温半田は取扱い
が面倒であるという難点がある。さらに、上記従
来の方法では量産性に適さず、コスト高となるは
免がれない。 As a conventional method for manufacturing a semiconductor device, for example, the method shown in FIG. 1 is known. In this method, as shown in FIGS. 1A to 1D, first, a plurality of circuit boards 1
Each component 2 is mounted on the substrate by, for example, a solder printing method or a reflow method using a substrate depth. 3 is a terminal portion of the wiring pattern. On the other hand, a predetermined jig 4 is prepared in advance in which a plurality of terminal pins 5 are arranged at equal intervals so as to correspond to each circuit board 1. In this state, each terminal pin 5 is soldered to the terminal portion 3 of the respective circuit board 1, and then resin molding is performed. 6 is solder. However, the hybrid integrated circuit manufactured by such a method has a drawback that the thermal strength of the terminal pins 5 is weak. That is, the hybrid integrated circuit obtained in this way is then mounted on a motherboard such as a printed circuit board by soldering to obtain a desired semiconductor device, but the soldering heat at this time causes the terminals in the hybrid integrated circuit to The solder between the pin 5 and the terminal portion 3 melts, causing problems such as the terminal pin being displaced. In order to overcome this drawback, it is conceivable to use high-temperature solder as the solder used to connect the terminal pins 5 and terminal portions 3 in the hybrid integrated circuit, but high-temperature solder has the disadvantage that it is troublesome to handle. Furthermore, the conventional method described above is not suitable for mass production and inevitably increases costs.
本発明は、上述の点に鑑み、従来の欠点を解消
し、量産化を可能にし、且つ信頼性を高めた半導
体装置の製造方法を提供するものである。 In view of the above-mentioned points, the present invention provides a method for manufacturing a semiconductor device that eliminates the conventional drawbacks, enables mass production, and improves reliability.
以下、本発明の一例を第2図を参照しながら説
明する。図において、1は回路基板を示し、例え
ばアルミナ基板、ガラスエポキシ基板等の絶縁基
板の一面に所望パターンの配線が形成されるその
各端子部3が基板の一側に延長されて構成され
る。本発明においては、先づ第2図A及びA′に
示すように例えば0.2〜0.4mm厚のリン青銅より成
り、複数の端子ピン8が所定時間をもつて一方向
に配列され各一端が連結部9にて連結された櫛歯
形のリードフレーム7を設ける。各端子ピン8の
遊端8aは第3図A及びBに示すように両側の爪
部10a,10bと中央の爪部10cとで挾持で
きるような所謂クリツプ構造に形成する。そし
て、このリードフレーム7に対して複数の回路基
板1を、その端子ピン8の遊端8aに基板の端子
部3が挾持的に嵌着されるように取付ける。この
回路基板1の端子ピン8への嵌着は自動機によつ
て1枚づつ行うようにしても良く、或は複数枚同
時に行うようにしてもよい。又、この場合、後述
で明らかとなるが各回路基板に連結された複数の
端子ピンのうち、1本の端子ピンは不要ピンで後
工程の際の回路基板の支持に使われるものであ
り、端子部3には接続されない。 An example of the present invention will be described below with reference to FIG. In the figure, reference numeral 1 denotes a circuit board, and each terminal portion 3 of the circuit board, on which a desired pattern of wiring is formed on one surface of an insulating substrate such as an alumina substrate or a glass epoxy substrate, extends to one side of the substrate. In the present invention, first, as shown in FIGS. 2A and A', a plurality of terminal pins 8 are made of phosphor bronze with a thickness of 0.2 to 0.4 mm, are arranged in one direction for a predetermined period of time, and each end is connected. A comb-shaped lead frame 7 connected at a portion 9 is provided. As shown in FIGS. 3A and 3B, the free end 8a of each terminal pin 8 is formed into a so-called clip structure so that it can be held by claws 10a, 10b on both sides and a center claw 10c. A plurality of circuit boards 1 are attached to this lead frame 7 so that the terminal portions 3 of the boards are clamped onto the free ends 8a of the terminal pins 8. The circuit board 1 may be fitted onto the terminal pins 8 one by one by an automatic machine, or a plurality of circuit boards 1 may be fitted simultaneously. Furthermore, in this case, as will become clear later, one terminal pin among the plurality of terminal pins connected to each circuit board is an unnecessary pin and is used to support the circuit board during post-processing. It is not connected to the terminal section 3.
次に、基板の各端子部3と各端子ピン8の遊端
8aとの半田付けを行うためにその部分にフラツ
クスを塗布して半田デツプを行う。11は半田で
ある。(第2図B及びB′)
次に、半田付けした端子ピンにおいて、その端
子部3と接続された端子ピン8のうちの1本例え
ば端子ピン8N、端子部3と接続されない不要な
端子ピン8Mを残して他の端子ピン8を連結部7
より切断し電気的、機械的に分離する。この場
合、各回路基板1は2本の端子ピン8N及び8M
によつて安定して支持される。又、残つた端子ピ
ン8Nは、各回路基板1において同じ位置のもの
とし、即ち同電位例えばアース電位が与えられる
ような端子ピンとする。そして、この状態におい
て、各回路基板1に対して夫々所定の部品2をマ
ウントする(第2図C)。 Next, in order to solder each terminal portion 3 of the board to the free end 8a of each terminal pin 8, flux is applied to that portion to form a solder depth. 11 is solder. (Fig. 2 B and B') Next, among the soldered terminal pins, one of the terminal pins 8 connected to the terminal part 3, for example, the terminal pin 8N, and an unnecessary terminal pin that is not connected to the terminal part 3. Leave 8M and connect the other terminal pins 8 to the connecting part 7.
Cut and separate electrically and mechanically. In this case, each circuit board 1 has two terminal pins 8N and 8M.
It is stably supported by Further, the remaining terminal pins 8N are at the same position on each circuit board 1, that is, they are terminal pins to which the same potential, for example, the ground potential is applied. In this state, predetermined components 2 are mounted on each circuit board 1 (FIG. 2C).
部品2をマウントして後に各回路基板に対して
動作チエツクを行う。この場合、各回路基板1に
於て1本の必要端子ピン8Nだけが連結部7を介
して互に共通接続されているので、この連結部7
を利用することによつて容易に動作チエツクが可
能となる。又、部品2のマウント及び動作チエツ
クが全て端子ピン8のピツチで位置決定されて行
えるので、リードフレーム7に設けた等ピツチの
透孔hを利用して自動化が容易となる。 After mounting the parts 2, an operation check is performed on each circuit board. In this case, since only one necessary terminal pin 8N on each circuit board 1 is commonly connected to each other via the connecting portion 7, this connecting portion 7
By using this, it is possible to easily check the operation. Further, since the mounting of the component 2 and the operation check can all be performed by determining the position by the pitch of the terminal pins 8, automation is facilitated by utilizing the equally pitched through holes h provided in the lead frame 7.
次に、各回路基板1を部品2と共に樹脂モール
ド12を施し、残つた端子ピン8N及び8Mを連
結部7より切断して混成集積回路13を得る(第
2図D)。 Next, each circuit board 1 is molded with a resin mold 12 together with the component 2, and the remaining terminal pins 8N and 8M are cut from the connecting portion 7 to obtain a hybrid integrated circuit 13 (FIG. 2D).
更に、斯くして得られた混成集積回路13をプ
リント基板等のマザーボードにマウントする。即
ち、第4図Aに示す如く、先に回路基板1の支持
として用い、既に不要となつた端子ピン8Mを所
定長さのところから略直角に折り曲げ、その状態
で第4図Bに示す如く混成集積回路13の各端子
ピン8をマザーボード14の各挿通孔15に挿通
せしめる。このとき混成集積回路は折り曲げられ
た不要端子ピン8Mによりマザーボート14の面
より所定位置に保持され、それ以上の端子ピン8
の挿入しすぎが防止され、又不要端子ピンの折り
曲げ部によつて混成集積回路13の倒れが防止さ
れる。さらには、他の挿通孔に対する誤挿入が防
止される。従つて、この状態で半田デツプを行え
ば、混成集積回路13のマザーボード14に対す
るマウントが良好に行える。その他、第5図に示
すように不要端子ピン8Mを所定長さに切断し誤
挿入防止及び挿入しすぎ防止を行うようにしても
よく、さらには第6図に示すようにマザーボード
14に穴16を設け、不要端子ピン8Mを所定形
状に切断し穴16に入れるようにする場合も考え
られる。このようにして目的とする半導体装置が
得られる。 Furthermore, the hybrid integrated circuit 13 thus obtained is mounted on a motherboard such as a printed circuit board. That is, as shown in FIG. 4A, the terminal pin 8M, which was used to support the circuit board 1 and is no longer needed, is bent at a substantially right angle from a predetermined length, and in that state, as shown in FIG. 4B. Each terminal pin 8 of the hybrid integrated circuit 13 is inserted into each insertion hole 15 of the motherboard 14. At this time, the hybrid integrated circuit is held at a predetermined position from the surface of the motherboard 14 by the bent unnecessary terminal pins 8M, and any further terminal pins 8M
This prevents excessive insertion of the terminal pins, and also prevents the hybrid integrated circuit 13 from falling due to the bent portions of the unnecessary terminal pins. Furthermore, incorrect insertion into other insertion holes is prevented. Therefore, if soldering is performed in this state, the hybrid integrated circuit 13 can be mounted on the motherboard 14 satisfactorily. In addition, as shown in FIG. 5, the unnecessary terminal pins 8M may be cut to a predetermined length to prevent incorrect insertion and over-insertion. Furthermore, as shown in FIG. It is also conceivable that the unnecessary terminal pin 8M is cut into a predetermined shape and inserted into the hole 16. In this way, the desired semiconductor device is obtained.
上述せる本発明によれば、半導体装置における
端子ピン8の信頼性が向上し、且つかかる半導体
装置の量産化が可能となる。すなわち、端子ピン
8はクリツプ構造をもつて回路基板1の端子部3
を挾持し、その上で半田付けされるので、爾後混
成集積回路をマザーボード14に半田付けによつ
てマウントする場合の耐熱性が向上し、半田時の
熱で混成集積回路における端子ピン8と端子部3
間の接続関係がずれることがない。又、リードフ
レーム7をキヤリアとして一連の工程が全て自動
化できるので量産化ができコスト低下が図れる。
さらに、部品をマウントしてからの動作チエツク
が可能となるのでさらに量産化、自動化を容易な
らしめる。 According to the present invention described above, the reliability of the terminal pins 8 in a semiconductor device is improved, and such semiconductor devices can be mass-produced. That is, the terminal pin 8 has a clip structure and is attached to the terminal portion 3 of the circuit board 1.
Since the hybrid integrated circuit is sandwiched and soldered thereon, heat resistance is improved when the hybrid integrated circuit is subsequently mounted on the motherboard 14 by soldering, and the heat during soldering can cause the terminal pin 8 of the hybrid integrated circuit to Part 3
The connection relationship between them will not shift. Furthermore, since the entire series of steps can be automated using the lead frame 7 as a carrier, mass production can be achieved and costs can be reduced.
Furthermore, since it is possible to check the operation of the parts after mounting them, mass production and automation are further facilitated.
第1図A〜Dは従来の製法を示す工程図、第2
図A〜Dは本発明による製法の一例を示す工程
図、第2図A′及びB′は夫々第2図A及びBの断
面図、第3図A及びBは本発明の端子ピンの例を
示す拡大平面図及びその側面図、第4図A及びB
は本発明で得た混成集積回路をマザーボードにマ
ウントする場合の工程図、第5図及び第6図は
夫々混成集積回路をマザーボードにマウントする
場合の他の例を示す斜視図である。
1は回路基板、2は部品、7はリードフレー
ム、8は端子ピンである。
Figures 1 A to D are process diagrams showing the conventional manufacturing method, Figure 2
Figures A to D are process diagrams showing an example of the manufacturing method according to the present invention, Figures 2 A' and B' are sectional views of Figures 2 A and B, respectively, and Figures 3 A and B are examples of the terminal pin of the present invention. An enlarged plan view and a side view thereof, FIGS. 4A and B
5 is a process diagram for mounting the hybrid integrated circuit obtained according to the present invention on a motherboard, and FIGS. 5 and 6 are perspective views showing other examples of mounting the hybrid integrated circuit on a motherboard, respectively. 1 is a circuit board, 2 is a component, 7 is a lead frame, and 8 is a terminal pin.
Claims (1)
てなる半導体装置の製造方法において、 複数の端子ピンが夫々1端で連結部を介して連
結されてなる櫛歯形リードフレームの該端子ピン
に対して複数の回路基板を接続する工程と、 上記各回路基板に対応して少くとも2本の端子
ピンを残して他の端子ピンを上記連結部より分離
する工程と、 上記連結部を利用して部品がマウントされた上
記回路基板に対して動作チエツクを行なう工程
と、 残された上記の少なくとも1本の端子ピンを上
記連結部より分離する工程と、 上記回路基板とは電気的に接続されていない少
くとも1本の端子ピンにより上記回路基板よりな
る混成集積回路をマザーボードに対して位置決め
する工程と、 上記混成集積回路を上記マザーボードにマウン
トする工程 を有する半導体装置の製造方法。[Claims] 1. A method for manufacturing a semiconductor device in which a hybrid integrated circuit is attached to a motherboard, comprising: a comb-shaped lead frame in which a plurality of terminal pins are connected at one end via a connecting portion; a step of connecting a plurality of circuit boards to the circuit board; a step of separating the other terminal pins from the connecting portion, leaving at least two terminal pins corresponding to each of the circuit boards; and utilizing the connecting portion. a step of performing an operation check on the circuit board on which the components are mounted; a step of separating the remaining at least one terminal pin from the connecting portion; and a step of electrically connecting the circuit board with the circuit board. A method for manufacturing a semiconductor device, comprising: positioning a hybrid integrated circuit made of the circuit board with respect to a motherboard using at least one terminal pin that is not connected to the circuit board; and mounting the hybrid integrated circuit on the motherboard.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9077378A JPS5518034A (en) | 1978-07-25 | 1978-07-25 | Method of fabricating hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9077378A JPS5518034A (en) | 1978-07-25 | 1978-07-25 | Method of fabricating hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5518034A JPS5518034A (en) | 1980-02-07 |
JPS6130745B2 true JPS6130745B2 (en) | 1986-07-15 |
Family
ID=14007915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9077378A Granted JPS5518034A (en) | 1978-07-25 | 1978-07-25 | Method of fabricating hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5518034A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6411446U (en) * | 1987-07-09 | 1989-01-20 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57190339A (en) * | 1981-05-19 | 1982-11-22 | Pioneer Electronic Corp | Manufacture of printed circuit board unit |
JPS58147138A (en) * | 1982-02-26 | 1983-09-01 | Hitachi Condenser Co Ltd | Manufacture of printed circuit board |
JPS6364349A (en) * | 1986-09-04 | 1988-03-22 | Sharp Corp | Manufacture of semiconductor device |
WO2014021212A1 (en) * | 2012-07-31 | 2014-02-06 | 株式会社村田製作所 | Manufacturing method for actuator device, and actuator device |
-
1978
- 1978-07-25 JP JP9077378A patent/JPS5518034A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6411446U (en) * | 1987-07-09 | 1989-01-20 |
Also Published As
Publication number | Publication date |
---|---|
JPS5518034A (en) | 1980-02-07 |
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