JPS6130402B2 - - Google Patents
Info
- Publication number
- JPS6130402B2 JPS6130402B2 JP55156970A JP15697080A JPS6130402B2 JP S6130402 B2 JPS6130402 B2 JP S6130402B2 JP 55156970 A JP55156970 A JP 55156970A JP 15697080 A JP15697080 A JP 15697080A JP S6130402 B2 JPS6130402 B2 JP S6130402B2
- Authority
- JP
- Japan
- Prior art keywords
- bit
- resistance
- resistor
- thin film
- contact resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010409 thin film Substances 0.000 claims description 18
- 238000010586 diagram Methods 0.000 description 6
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 229910001120 nichrome Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Non-Adjustable Resistors (AREA)
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
この発明は、薄膜ラダー抵抗網回路の温度特性
のマツチング精度を向上することに関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the matching accuracy of the temperature characteristics of a thin film ladder resistor network circuit.
さらに詳細に言うならば、デジタル―アナログ
変換器（以下、Ｄ―Ａ変換器という）を構成する
薄膜ラダー抵抗網に関し、各ビツト電流の重みづ
けに対応するビツト抵抗に対して、電極との接触
部で存在する接触抵抗の占める割合を制御して、
各ビツト抵抗の相対温度係数のマツチングを得る
ことを特徴とする薄膜ラダー抵抗網回路を提供す
ものである。 More specifically, regarding the thin film ladder resistance network that constitutes a digital-to-analog converter (hereinafter referred to as a DA converter), contact with the electrode is determined for the bit resistance corresponding to the weighting of each bit current. By controlling the proportion of contact resistance present in the
A thin film resistor ladder network circuit is provided which is characterized by obtaining a matching of the relative temperature coefficients of each bit resistor.
Ｄ―Ａ変換器における最も重要な特性である非
直線性誤差は、使用温度範囲全体にわたつて、そ
の必要精度を維持し、保証しなければならない。 Nonlinearity error, which is the most important characteristic in a DA converter, must maintain and guarantee its required accuracy over the entire operating temperature range.
そして、この非直線性誤差の温度特性を表現す
る基本式は、ラダー抵抗網の相対温度特性そのも
のと、定電流トランジスタおよびスイツチングト
ランジスタのビツト間マツチングに関するものと
で成立していることが発明者らによつて求められ
ている。 The inventors discovered that the basic equation expressing the temperature characteristics of this nonlinearity error is established by the relative temperature characteristics of the ladder resistance network itself and the bit-to-bit matching of constant current transistors and switching transistors. It is required by the following.
従つて、ビツト間相対温度特性に本質的に関係
するデバイスパラメータの一つとして、ビツト抵
抗の相対温度係数のマツチング精度を高める必要
がある。 Therefore, it is necessary to improve the matching accuracy of the relative temperature coefficient of bit resistance, which is one of the device parameters essentially related to the relative temperature characteristics between bits.
特に、12ビツトを超えるような比較的高精度の
Ｄ―Ａ変換器にあつては、このビツト抵抗の相対
温度係数のマツチングを必要かつ十分に保つこと
が重要な課題となる。 Particularly in the case of relatively high-precision DA converters exceeding 12 bits, it is an important issue to maintain necessary and sufficient matching of the relative temperature coefficients of the bit resistances.
しかるに、従来の薄膜ラダー抵抗網回路におい
ては、各ビツト抵抗の相対温度係数のマツチング
を容易に高める技術が明らかでなく、シート抵抗
（Ω/□）の小さいNiCrなどの薄膜抵抗で、数ｋ
Ωの抵抗値を得るジグザク模様のパターンで形成
したビツト抵抗の相対温度係数のマツチングを実
現することが、非常に困難である欠点があつた。 However, in the conventional thin film ladder resistor network circuit, there is no clear technology to easily improve the matching of the relative temperature coefficient of each bit resistor, and thin film resistors such as NiCr with low sheet resistance (Ω/□) can be used to
A drawback is that it is extremely difficult to match the relative temperature coefficients of bit resistances formed in a zigzag pattern to obtain a resistance value of Ω.
この従来の薄膜ラダー抵抗網について、第１図
と第２図によつて説明する。 This conventional thin film ladder resistor network will be explained with reference to FIGS. 1 and 2.
第１図は、Si基板１上に通常の薄膜技術を用い
て形成したNiCr抵抗２およびAl電極３を示す。
ここでは、130Ω/□のシート抵抗を有するNiCr
薄膜によつて形成された、8kΩ，16kΩ，32kΩ
のビツト１〜ビツト３の高位ビツト抵抗の一部を
示すものである。これらの抵抗幅は、W1＝W2＝
W325μｍである。抵抗長は、機能修正のための
調整部Ａを含むパターンとして、通常の計算式に
よつて、その有効長が求められている。 FIG. 1 shows a NiCr resistor 2 and an Al electrode 3 formed on a Si substrate 1 using conventional thin film technology.
Here, NiCr with sheet resistance of 130Ω/□
8kΩ, 16kΩ, 32kΩ formed by thin film
This figure shows a part of the high-order bit resistance of bits 1 to 3. The width of these resistances is W 1 = W 2 =
W 3 is 25 μm. The effective length of the resistance length is determined by a normal calculation formula as a pattern including the adjustment part A for functional modification.
この第１図に示す各ビツト抵抗の温度係数測定
結果を第２図に示した。この結果から、明らかな
ごとくビツト抵抗の相対温度係数で、3ppm／℃
を超えるマツチングのづれを生じる欠点がある。
従来、この欠点を生ずる要因が明らかでなく、解
決策もないままに製造が行なわれていた。このた
め、12ビツトを超えるような比較的大きなデジタ
ルビツトのＤ―Ａ変換器を構成しても、非直線性
誤差の温度特性精度が低下する欠点を有するもの
であつた。 The temperature coefficient measurement results for each bit resistance shown in FIG. 1 are shown in FIG. From this result, it is clear that the relative temperature coefficient of bit resistance is 3ppm/℃.
This method has the disadvantage of causing mismatching that exceeds .
Conventionally, the factors causing this defect were not clear, and manufacturing was carried out without a solution. For this reason, even if a DA converter with relatively large digital bits exceeding 12 bits is configured, it has the disadvantage that the accuracy of the temperature characteristic of non-linearity error decreases.
本発明は、上述の欠点を改良するものであり、
以下第３図〜第６図に従つて説明する。 The present invention improves the above-mentioned drawbacks, and
This will be explained below with reference to FIGS. 3 to 6.
第３図は、本発明による薄膜ラダー抵抗網回路
で、熱酸化によるSiO2の絶縁膜が施されたSi基板
１上に蒸着法およびスパツタ法などによる通常の
薄膜技術を用いて形成したNiCr抵抗２およびAl
電極３を示すものである。 FIG. 3 shows a thin film ladder resistor network according to the present invention, in which a NiCr resistor is formed using ordinary thin film techniques such as evaporation and sputtering on a Si substrate 1 on which an insulating film of SiO 2 is applied by thermal oxidation. 2 and Al
Electrode 3 is shown.
ここでも、従来例と同じく130Ω/□のシート抵
抗を有するNiCr抵抗で形成した、8kΩ，16kΩ，
32kΩのビツト１〜ビツト３の高位ビツト抵抗を
示すものである。抗抗幅は、W1＝W2＝W3＝25μ
ｍとした。抵孔長は、機能修正のための調整部Ａ
を含むパターンで、通常の計算式によつて、その
有効長を求めた。この抵抗の有効長および抵抗幅
は、従来例と異なるところはない。 Here, as in the conventional example, 8kΩ, 16kΩ,
This shows the high bit resistance of bits 1 to 3 of 32kΩ. The resistance width is W 1 = W 2 = W 3 = 25μ
It was set as m. The resistance hole length is the adjustment part A for functional correction.
The effective length of the pattern was calculated using the usual calculation formula. The effective length and resistance width of this resistor are the same as those of the conventional example.
しかし、この第３図において、25μｍの抵抗幅
W1でAl電極３と接触する部分１個所で存在する
接触抵抗を、1Rcと仮定すると、ビツト１の抵抗
は、25μｍで幅で電極と接触する部分が４個所で
あることから、その接触抵抗の総数は4Rcであ
る。同様に、ビツト２の抵抗では、8Rc、ビツト
３の抵抗では、16Rcである。そして、この接触
抵抗の総数を各ビツト抵抗で除算したものを、各
ビツト抵抗のバルク抵抗値に対する接触抵抗の占
める比率（以下、接触抵抗比という）とすると、
ビツト１の接触抵抗比は、4Rc／8kΩ＝0.5Rc，
ビツト２では、8Rc／16kΩ＝0.5Rc，ビツト３で
は、16Rc／32kΩ＝0.5Rcとなる。 However, in this Figure 3, the resistance width of 25μm
Assuming that the contact resistance existing at one point in contact with the Al electrode 3 at W 1 is 1Rc, the resistance of bit 1 is 25 μm wide and there are 4 points in contact with the electrode, so the contact resistance is The total number of is 4Rc. Similarly, the resistance for bit 2 is 8Rc, and the resistance for bit 3 is 16Rc. Then, dividing this total number of contact resistances by each bit resistance is the ratio of the contact resistance to the bulk resistance value of each bit resistance (hereinafter referred to as contact resistance ratio).
The contact resistance ratio of bit 1 is 4Rc/8kΩ=0.5Rc,
For bit 2, 8Rc/16kΩ=0.5Rc, and for bit 3, 16Rc/32kΩ=0.5Rc.
この接触抵抗比が、従来例と異なるものであ
り、従来例について、これを求めると、ビツト１
の抵抗は、0.5Rc、ビツト２の抵抗は、
0.625Rc、ビツト３の抵抗は、0.375Rcであり、
本発明によるものと異なるのはビツト２およびビ
ツト３の抵抗の接触抵抗比である。 This contact resistance ratio is different from the conventional example, and when it is determined for the conventional example, it is bit 1.
The resistance of is 0.5Rc, and the resistance of bit 2 is
0.625Rc, the resistance of bit 3 is 0.375Rc,
What differs from the present invention is the contact resistance ratio of the resistances of bit 2 and bit 3.
そして、本発明による第３図の高位各ビツト抵
抗の温度係数測定結果を第４図に示し、上述の接
触抵抗比を第５図に示す。 FIG. 4 shows the temperature coefficient measurement results of each high-order bit resistance shown in FIG. 3 according to the present invention, and FIG. 5 shows the above-mentioned contact resistance ratio.
この第４図の結果から明らかなごとく、各ビツ
ト抵抗の相対温度係数のマツチングは著しく向上
する。 As is clear from the results shown in FIG. 4, the matching of the relative temperature coefficients of each bit resistance is significantly improved.
これは、第５図の接触抵抗比を示す結果が温度
係数測定結果との間に、明らかな相関関係をも
ち、各ビツト抵抗の接触抵抗比を制御することに
よつて、各ビツト抵抗の相対温度係数のマツチン
グ精度を高めることができることを証明している
ものである。 This is because the results showing the contact resistance ratio in Figure 5 have a clear correlation with the temperature coefficient measurement results, and by controlling the contact resistance ratio of each bit resistance, the relative This proves that it is possible to improve the matching accuracy of temperature coefficients.
すなわち各ビツト抵抗のバルク抵抗値に対する
接触抵抗比を等しくすることによつて良好な温度
特性のマツチングが得られるものである。 That is, by making the contact resistance ratio of each bit resistor to the bulk resistance value equal, good matching of temperature characteristics can be obtained.
そして、本発明者らの実験によつて、各ビツト
抵抗の接触抵抗比の差違による温度係数のマツチ
ングのずれ（ΔT.C.R）を求めた結果が第６図で
ある。 FIG. 6 shows the results of experiments conducted by the present inventors to determine the temperature coefficient matching deviation (ΔT.CR) due to the difference in the contact resistance ratio of each bit resistance.
各ビツト抵抗の接触抵抗比の差が、大きくなる
ほど、相対温度係数のマツチング精度が劣る傾向
が明らかである。 It is clear that the greater the difference in the contact resistance ratio of each bit resistance, the worse the matching precision of the relative temperature coefficient becomes.
このように、本発明の最大の特徴とするところ
は、各ビツト抵抗のバルク抵抗値に対する接触抵
抗の比率、すなわち接触抵挺抗比を等しく保つこ
とによつて、各ビツト抵抗の相対温度係数のマツ
チングをはかるものである。 As described above, the greatest feature of the present invention is that by keeping the ratio of the contact resistance to the bulk resistance of each bit resistance, that is, the contact resistance ratio, equal, the relative temperature coefficient of each bit resistance can be reduced. This is to measure matching.
したがつて、本発明による薄膜ラダー抵抗網回
路の相対温度係数のマツチング精度が高まり、こ
の薄膜ラダー抵挺抗網回路で構成されるＤ―Ａ変
換器の非直線性誤差の温度特性が保証され、精度
の高いＤ―Ａ変換器の製品化を容易ならしめると
同時に製造歩留りを向上させ得るなどの工業上非
常に大きな効果を発揮するものである。 Therefore, the accuracy of matching the relative temperature coefficients of the thin film ladder resistor network circuit according to the present invention is increased, and the temperature characteristics of the nonlinearity error of the DA converter configured with this thin film ladder resistor network circuit are guaranteed. This has great industrial effects, such as facilitating the commercialization of high-precision D-A converters and improving manufacturing yields.
第１図は、従来の薄膜ラダー抵抗網回路の一部
上面図、第２図は、その温度係数測定結果を示す
図、第３図は、本発明の一実施例における薄膜ラ
ダー抵抗網回路の一部上面図、第４図は、その温
度係数測定結果を示す図、第５図は、従来例ａと
本発明ｂによる各ビツト抵抗に対する接触抵抗比
を示す図、第６図は、本発明による接触抵抗比の
差と温度係数のミスマツチを示す図である。
１……Si基板、２……NiCr抵抗、３……Al電
極。
FIG. 1 is a partial top view of a conventional thin film ladder resistor network circuit, FIG. 2 is a diagram showing the temperature coefficient measurement results, and FIG. 3 is a diagram of a thin film ladder resistor network circuit according to an embodiment of the present invention. A partial top view, FIG. 4 is a diagram showing the temperature coefficient measurement results, FIG. 5 is a diagram showing the contact resistance ratio for each bit resistance according to the conventional example a and the present invention b, and FIG. 6 is a diagram showing the present invention FIG. 3 is a diagram showing a difference in contact resistance ratio and a mismatch in temperature coefficient due to the difference in contact resistance ratio. 1...Si substrate, 2...NiCr resistor, 3...Al electrode.
Claims (1)
ダー抵抗において、各ビツト抵抗を形成するバル
ク抵抗およびバルク抵抗と電極との接触する部分
において存在する接触抵抗に関し、前記接触抵抗
がバルク抵抗に対して占める比率（接触抵抗比）
を各ビツト抵抗に対し互いに等しくしたことを特
徴とするビツト抵抗で構成する薄膜ラダー抵抗網
回路。 ２ 前記ビツト抵抗がＵ形パターンの繰返しであ
るジグザク模様のパターンで形成した薄膜抵抗で
ある特許請求の範囲第１項記載の薄膜ラダー抵抗
網回路。[Scope of Claims] 1. In a thin film ladder resistor constituting a digital-to-analog converter, with respect to the bulk resistor forming each bit resistor and the contact resistance existing in the contact portion between the bulk resistor and the electrode, the contact resistance is the bulk resistor. Ratio to resistance (contact resistance ratio)
A thin film ladder resistor network circuit comprising bit resistors, characterized in that the resistors are made equal to each other for each bit resistor. 2. The thin film ladder resistor network circuit according to claim 1, wherein the bit resistor is a thin film resistor formed in a zigzag pattern that is a repeating U-shaped pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55156970A JPS5780702A (en) | 1980-11-10 | 1980-11-10 | Thin film radar resistor network circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55156970A JPS5780702A (en) | 1980-11-10 | 1980-11-10 | Thin film radar resistor network circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5780702A JPS5780702A (en) | 1982-05-20 |
| JPS6130402B2 true JPS6130402B2 (en) | 1986-07-14 |
Family
ID=15639299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55156970A Granted JPS5780702A (en) | 1980-11-10 | 1980-11-10 | Thin film radar resistor network circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5780702A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04123120U (en) * | 1991-04-23 | 1992-11-06 | 池本刷子工業株式会社 | hair brush |
| US10889148B1 (en) * | 2019-07-06 | 2021-01-12 | John McGill | Airless tire |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5117817B2 (en) * | 2006-11-02 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | Multi-level voltage generator, data driver, and liquid crystal display device |
-
1980
- 1980-11-10 JP JP55156970A patent/JPS5780702A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04123120U (en) * | 1991-04-23 | 1992-11-06 | 池本刷子工業株式会社 | hair brush |
| US10889148B1 (en) * | 2019-07-06 | 2021-01-12 | John McGill | Airless tire |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5780702A (en) | 1982-05-20 |
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