JPS6116562A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6116562A JPS6116562A JP13830484A JP13830484A JPS6116562A JP S6116562 A JPS6116562 A JP S6116562A JP 13830484 A JP13830484 A JP 13830484A JP 13830484 A JP13830484 A JP 13830484A JP S6116562 A JPS6116562 A JP S6116562A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicate glass
- nsg
- thin
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はディジタル−アナログ変換器（以下、ＤＡＣと
いう）などに用いられる高精度の薄膜抵抗回路を有する
半導体に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor having a highly accurate thin film resistance circuit used in a digital-to-analog converter (hereinafter referred to as DAC).
従来例の構成とその問題点
一般に、ＤＡＣにおいては、薄膜抵抗回路に形成した各
ビット電流の重みづけに対応する薄膜ラダー抵抗の抵抗
値調整によって高精度化をはかつている。Conventional Structures and Problems Generally, in a DAC, high accuracy is achieved by adjusting the resistance value of a thin film ladder resistor formed in a thin film resistor circuit corresponding to the weighting of each bit current.
この抵抗値調整は、はとんどがレーザ光を用いた機能ト
リミング（以下、レーザトリミングという）で行なわれ
ているが、１２ビットヲ超えるような高精度のＤＡＣに
対しては、必要かつ十分な性能を再現するレーザトリミ
ングが要求される。This resistance value adjustment is mostly performed by functional trimming using laser light (hereinafter referred to as laser trimming), but it is necessary and sufficient for high-precision DACs exceeding 12 bits. Laser trimming is required to reproduce performance.
しかも、ＤＡＣの変換性能は、使用される周囲環境条件
の全体にわたって、その必要精度を維持する高信頼性を
保証しなければならない。Moreover, the conversion performance of the DAC must ensure high reliability, maintaining its required accuracy over the entire range of ambient conditions in which it is used.
しかし、その精度を十分に高めること、およびその必要
精度を維持し得る信頼性を確保することは容易でない。However, it is not easy to sufficiently increase the accuracy and ensure reliability that can maintain the required accuracy.
なぜなら、薄膜抵抗回路に用いて構成する高精度のＤＡ
Ｃにおいては、薄膜抵抗回路を湿気、塵埃、不純物イオ
ンなどの外部汚染から保護する目的で、回路を覆って形
成するパッシベーション膜が不可欠であるが、このパッ
シベーション膜によって、信頼性を確保できない欠点や
レーザトリミングの加工精度の低下や困難さを生じる欠
点を有している。This is because high-precision DA constructed using thin film resistance circuits
In order to protect the thin film resistor circuit from external contamination such as moisture, dust, impurity ions, etc., a passivation film is required to cover the circuit. This method has the disadvantage of reducing processing accuracy and making laser trimming difficult.
この従来例について、基準電圧源回路や電流スイッチン
グ回路など周知の半導体集積回路技術を用いて形成する
能動的回路（以下、半導体回路という）と各ビット電流
の重みづけに対応するラダー抵抗網回路など、周知の薄
膜形成技術を用いて形成する薄膜抵抗回路が一体化構成
されたモノリシックＤＡＣ’（ｉ７具体例にして、第１
図を参照して説明する。Regarding this conventional example, active circuits (hereinafter referred to as semiconductor circuits) formed using well-known semiconductor integrated circuit technology such as reference voltage source circuits and current switching circuits, and ladder resistance network circuits that correspond to weighting of each bit current, etc. , a monolithic DAC' (i7 specific example, the first
This will be explained with reference to the figures.
第１図はＤＡＣチップ１１の断面図である。周知のバイ
ポーラ集積回路製造技術を用いて、半導体基板２、たと
えば、シリコン゛（Ｓｔ ）の内部に半導体素子３を形
成した後、その表面に、絶縁膜４、たとえば、二酸化シ
リコン（ＳｉＯ２）膜を形成し、ついでこの上にＮｉ
−Ｃｒ 系合金やＳｉ −Ｃｒ 系合金などの薄膜抵抗
素子６を形成し、さらに、それらの素子を電気的に接続
して回路構成するためのＭ配線６を形成する。そして、
この半導体回路や薄膜抵抗回路を外部汚染から保護する
ために、全回路要素面を覆って、ＳｉＯ２あるいは窒化
シリコン（ＳｉＮ）または５１０２とＳｉＮとの二層パ
ッシベーション膜７のいづれかが選択されて形成される
。FIG. 1 is a cross-sectional view of the DAC chip 11. After forming a semiconductor element 3 inside a semiconductor substrate 2, such as silicon (St), using a well-known bipolar integrated circuit manufacturing technique, an insulating film 4, such as a silicon dioxide (SiO2) film, is formed on the surface thereof. formed, and then Ni
A thin film resistance element 6 made of a -Cr alloy or a Si-Cr alloy is formed, and an M wiring 6 for electrically connecting these elements to form a circuit is formed. and,
In order to protect this semiconductor circuit and thin film resistance circuit from external contamination, either SiO2, silicon nitride (SiN), or a two-layer passivation film 7 of 5102 and SiN is selected and formed to cover all circuit element surfaces. Ru.
しかしながら、上述のＳ ｉｏ２． Ｓ ｉＮ 、Ｓ
ｉｏ２＋Ｓ ｉＮのパッシベーション膜下は多くの問題
をかかえてい６０例エバ、５１０２ハノシベーション膜
ｔｏ、６〜１．６μの厚さで形成したＤＡＣにあっては
、薄膜抵抗回路に形成された薄膜ラダー抵抗のレーザト
リミングは、容易に十分な加工条件が求められ、しかも
安定に変換精度を高めることができる長所を有している
ものの、このＤＡＣチップを樹脂封止パッケージに実装
して、温度８５℃の高温通電試験や１２１℃、２気圧の
プレッシャークツカー試験などの加速寿命試験を実施す
ると、薄膜抵抗回路にあるＮｉ −Ｃｒ 系合金または
、Ｃｒ−８ｉ 系合金の薄膜ラダー抵抗などの抵抗変化
率が時間と共に大きく増大し、レーザトリミングで得ら
れた精度を著しく変化せしめ、ＤＡＣ性能を劣化させる
ものであった。これらは、５ｉ０２ハノシベーシヨ膜が
ポーラスな膜質であったシ、クラックを生じやすいこと
などのため、十分なパッシベーション効果を発揮してい
ないことに起因している。However, the above-mentioned S io2. S iN , S
There are many problems under the passivation film of IO2+S iN.For DACs formed with a thickness of 6 to 1.6μ, the thin film ladder formed on the thin film resistor circuit. Laser trimming of resistors requires easy processing conditions and has the advantage of being able to stably improve conversion accuracy. When accelerated life tests such as high-temperature energization tests and pressure Kutzker tests at 121°C and 2 atmospheres are carried out, the rate of change in resistance of thin film ladder resistors made of Ni-Cr alloys or Cr-8i alloys in thin film resistor circuits is significantly reduced. increases significantly over time, significantly changing the accuracy obtained by laser trimming and degrading DAC performance. These problems are due to the fact that the 5i02 Hanoshiba film was porous and easily cracked, so it did not exhibit a sufficient passivation effect.
筺た、他の例として、ＳｉＮパッシベーション膜ヲ０．
２〜１．０μの厚さで形成し１ＤＡｃｖＣ，％つては、
薄膜抵抗回路にある薄膜ラダー抵抗のレーザトリミング
において、良好なトリミング加工条件が求められず、し
かも抵抗値調整の安定性に乏しいために、高精度のＤＡ
変換性能を実現できない。As another example, a SiN passivation film was used.
Formed with a thickness of 2 to 1.0μ, 1DAcvC,%,
Laser trimming of thin-film ladder resistors in thin-film resistor circuits does not require good trimming processing conditions, and the stability of resistance value adjustment is poor.
Conversion performance cannot be achieved.
これは、５ＩＯ２パツシベーシヨン膜に比較してＳｉＮ
パッシベーション膜の膜質が緻密で強固な密に
着力を有しているためＸこれが災いして、レーザトリミ
ングによって焼失するＮｉ −Ｃｒ 系または５ｉ−Ｃ
ｒ系の薄膜抵抗体材料の拡散現象を抑圧していることに
起因して、十分に精度を高めるレーザトリミングを阻害
しているものと考えられる。This is compared to the 5IO2 passivation film.
Because the film quality of the passivation film is dense and has strong adhesion, this causes the Ni-Cr series or 5i-C to be burned out during laser trimming.
It is thought that the suppression of the diffusion phenomenon of the r-based thin film resistor material inhibits laser trimming to sufficiently improve accuracy.
さらに、他の例として、５ｉｎ２＋ＳｉＮの二層構造の
パッシベーション膜？ ’ｃ し’ｃ’ し０．２〜０
．５μ。Furthermore, as another example, a passivation film with a two-layer structure of 5in2+SiN? 'c''c' shi0.2~0
．． 5μ.
０．２〜１．０μの厚さで形成したＤＡＣＫあっては、
前述のレーザトリミングの加工に関する問題は解決され
るものの、高温連続通電試験などに対して、レーザトリ
ミングによって得られたＤＡＣとしての高精度変換性能
が著しく劣化してしまう欠点を有している。これは、最
初に形成するＳ ｚ０２パッシベーション膜中または膜
表面に吸着した水分や不純物イオンがその上に形成した
ＳｉＮパッシベーション膜により封じ込められてしまう
ことによるものと考えられる。For DACK formed with a thickness of 0.2 to 1.0μ,
Although the above-mentioned problems related to laser trimming processing are solved, there is a drawback that the high-precision conversion performance as a DAC obtained by laser trimming is significantly degraded in high-temperature continuous energization tests and the like. This is considered to be due to the fact that moisture and impurity ions adsorbed in or on the surface of the Sz02 passivation film formed first are confined by the SiN passivation film formed thereon.
以上の説明から明らかなように、従来の３１０２やＳｉ
Ｎパッシベーション膜を形成した薄膜抵抗回路を用いた
ＤＡＣなどで、その精度を十分に高めること、および信
頼性の保証には一長一短があり、製品化の実現を困難に
していた。As is clear from the above explanation, conventional 3102 and Si
There are advantages and disadvantages in sufficiently increasing the precision and guaranteeing reliability of DACs and the like that use thin-film resistor circuits with N passivation films, making it difficult to commercialize them.
発明の目的
本発明はこのような従来技術の問題点を解消し高精度化
および、信頼性の保証を可能とした薄膜抵抗回路を有す
る半導体装置を提供するものであるＯ
発明の構成
本発明は、上記目的を達成するため、基板上に形成され
た薄膜抵抗素子の上部にノンドーグシリケートガラス（
以下、ＮＳＣという）パッシベーション膜と、更にこの
上にリンドソプシリケートガラス（以下ＰＳＧという）
パッシベーション膜と、更にこの上にＮ Ｓ Ｇ パッ
シベーション膜を形成して、Ｎ５Ｇ−ＰＳＧ−ＮＳＧの
三層をなしたものでアシ、これにより、高精度のレーザ
トリミング適応性ならびに信頼性の向上をはかることが
できる。OBJECTS OF THE INVENTION The present invention provides a semiconductor device having a thin film resistor circuit that solves the problems of the prior art and makes it possible to achieve high precision and guarantee reliability. , In order to achieve the above objective, a non-dogue silicate glass (
A passivation film (hereinafter referred to as NSC) and a lindsop silicate glass (hereinafter referred to as PSG) on top of this.
A passivation film and an NSG passivation film are formed on top of the passivation film to form a three-layer structure of N5G-PSG-NSG.This improves the adaptability and reliability of high-precision laser trimming. be able to.
実施例の説明
以下、本発明の実施例について、モノリクックＤＡＣｉ
具体例にして説明する。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described using a monolithic DACi.
This will be explained using a specific example.
第２図は、本発明の一実施例に係るモノリシックＤＡＣ
チップ２１の断面図である。同図において、８１ 基板
１２上に形成されたＮ型エビタキシル
１層の内部に、周知のバイポーラ集積回路技術を用いて
、基準電圧源回路や電流スイッチ回路々どを構成する半
導体素子１３を形成した後、この表面に８１０２膜１４
を形成し、さらに、このＳ １０２゜膜１４膜上にたと
えば電子ビーム蒸着法によって、Ｎｉ −Ｃｒ （８０
： ２０ ） ｆ抵抗材料として、１００〜２５０人の
厚みを有するＮｉ −Ｃｒ 系合金薄膜を形成する。そ
の後、通常のフォ） ＩＪソグラフィ技術を用いて、各
ビット電流の重みづけに対応するＲ−２Ｒ抵抗ネツトワ
ーク１５のパターン全形成する。なお、ここでは抵抗薄
膜材料にＮｉ −Ｃｒ ｆ使用したが、必要に応じてＳ
ｉ −Ｏｒ などの抵抗材料を使用してもよい。FIG. 2 shows a monolithic DAC according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the chip 21. FIG. In the figure, a semiconductor element 13 constituting a reference voltage source circuit, a current switch circuit, etc. is formed inside a single layer of N-type Ebitaxyl formed on a substrate 12 using well-known bipolar integrated circuit technology. After that, 8102 film 14 is applied to this surface.
Further, Ni-Cr (80
:20) Form a Ni--Cr based alloy thin film having a thickness of 100 to 250 mm as f-resistance material. Thereafter, the entire pattern of the R-2R resistor network 15 corresponding to the weighting of each bit current is formed using conventional photo-IJ lithography techniques. Although Ni-Crf was used here as the resistive thin film material, S
Resistive materials such as i-Or may also be used.
そして、これら半導体素子および薄膜抵抗素子などを電
気的に接続し、回路構成するためのアルミニウム配線パ
ターン１６を形成する。Then, an aluminum wiring pattern 16 is formed to electrically connect these semiconductor elements, thin film resistance elements, etc. to form a circuit.
次に、この半導体回路と薄膜抵抗回路を覆って保護する
ために、常圧または減圧ＣＶＤ法によって、ＮＳＧパッ
シベーション膜１日を１６００〜４０００人、ついで、
リンを約４重量％含有するＰＳＧパッシベーション膜１
９’１１５００〜６０００人の厚みで、さらに、ＮＳＧ
パッシベーション膜２０’１１５００〜４０００Ａの厚
みで連続的に成長させる。そしてこの三層パッシベーシ
ョン膜の一部をワイヤボンディング用窓を開口した後、
４６０℃のＮ２雰囲気中で熱処理を施して、ウェノ蔦一
工程カニ完了する。Next, in order to cover and protect this semiconductor circuit and thin film resistance circuit, an NSG passivation film was applied to 1,600 to 4,000 people per day using normal pressure or low pressure CVD.
PSG passivation film 1 containing about 4% by weight of phosphorus
With a thickness of 9'11500 to 6000 people, in addition, NSG
The passivation film 20' is continuously grown to a thickness of 11500 to 4000A. After opening a window for wire bonding in a part of this three-layer passivation film,
A heat treatment is performed in a N2 atmosphere at 460° C. to complete the first step of making the wenotsuta crab.
この後、す、上の工程で製造したモノリシックＤＡＣの
変換性能を十分に高精度化するために、薄膜抵抗回路に
形成した薄膜ラダーネットワークの抵抗値調整を行うレ
ーザトリミングを実施した〇本発明の薄膜抵抗回路では
、Ｎｉ −Ｃｒ 系合金の薄膜抵抗素子上にＮＳＧ＋Ｐ
ＳＧ＋ＮＳＧ の三層構造の保護膜を被覆したことによ
り、レーザトリミングによって焼失するＮｉ −Ｃｒ
系合金の薄膜材料がＮＳＧ膜中に容易に拡散できるため
、安定な抵抗値調整が５Ｔ能となシ、ＤＡＣとしての高
精度の変換性能を実現できる。After this, in order to sufficiently improve the conversion performance of the monolithic DAC manufactured in the above process, laser trimming was performed to adjust the resistance value of the thin film ladder network formed in the thin film resistor circuit. In a thin film resistance circuit, NSG+P is placed on a Ni-Cr alloy thin film resistance element.
By coating the protective film with a three-layer structure of SG+NSG, the Ni-Cr that is burnt out during laser trimming is removed.
Since the thin film material of the alloy can be easily diffused into the NSG film, stable resistance value adjustment is possible with 5T performance, and high precision conversion performance as a DAC can be achieved.
更に、本実施例のモノリシックＤＡＣチップを従来例と
同様に樹脂封止パッケージに実装して、高温連続通電テ
ストやプレノシャークッカーテストヲ実施した結果、薄
膜抵抗回路にあるＮｉ −Ｃｒ系合金の薄膜ラダー抵抗
の抵抗変化率は著しく小さく、非常に安定しているもの
であった。このため、レーザトリミングによって得られ
た高精度のＤＡ変換性能を長時間にわたって維持し、保
証できることを確認した。Furthermore, the monolithic DAC chip of this example was mounted in a resin-sealed package in the same manner as the conventional example, and as a result of conducting a high-temperature continuous energization test and a Planosha cooker test, it was found that the Ni-Cr alloy in the thin film resistance circuit was The resistance change rate of the thin film ladder resistor was extremely small and very stable. Therefore, it was confirmed that the highly accurate DA conversion performance obtained by laser trimming can be maintained and guaranteed for a long time.
このように、本発明の薄膜抵抗回路はＮ Ｓ Ｇ 十Ｐ
ＳＧ＋ＮＳＧ の３層のパッシベーション膜ヲ形成す
ることによって、レーザトリミングの加工精練全向上さ
せるとともに、保護膜中の水分や不純物イオンの除去や
ゲッター効果を有するだけでなく、外部汚染から回路全
十分保護するパッシベーション膜果をも著しく向上させ
得る特徴を発揮するものである。In this way, the thin film resistor circuit of the present invention has N S G
By forming a three-layer passivation film of SG+NSG, it not only improves the processing quality of laser trimming, removes moisture and impurity ions in the protective film, and has a getter effect, but also sufficiently protects the entire circuit from external contamination. It exhibits characteristics that can significantly improve passivation film performance.
なお、上述した実施例では、パッシベーション膜の形成
を常圧または、減圧ＣＶＤ法によって実施したが、本発
明はこの形成法に限定されるものではなく、プラズマＣ
ＶＤ法やスパッタ法などの他の形成法によって形成した
ものにも適用が可能である。In the above embodiments, the passivation film was formed by normal pressure or low pressure CVD, but the present invention is not limited to this method.
It is also applicable to those formed by other forming methods such as the VD method and the sputtering method.
１だ、実施例で（ｄ二モノリシックＤＡＣの薄膜抵抗回
路について説明したが、本発明の要旨はこれに限定され
るものではなく、薄膜抵抗回路を用いる他の電子部品に
おいても同様に成立するものである。1. Although the thin film resistance circuit of a monolithic DAC was explained in the example (d2), the gist of the present invention is not limited to this, and the present invention can similarly be applied to other electronic components using a thin film resistance circuit. It is.
発明の効果
以上の説明のごとく、本発明はＤＡＣなどに用いられる
薄膜抵抗回路において、この回路上に、ＮＳＧ＋ＰＳＧ
＋ＮＳＧパッシベーション膜を形成することによって、
高精度のレーザトリミングを可能にし、更にこの高精度
の抵抗性能？保証する高信頼性を実現し得るものであシ
、工業上非常に大きな効果を発揮するものである。Effects of the Invention As explained above, the present invention provides a thin film resistor circuit used for DAC etc., in which NSG+PSG
+By forming a NSG passivation film,
Is this high-precision resistor performance possible, as well as high-precision laser trimming? It is possible to achieve guaranteed high reliability, and it has a very large industrial effect.
第１図は従来の薄膜抵抗回路を用いたモノリシックＤＡ
Ｃのチップ断面構造図、第２図は本発明の一実施例を用
いたモノリシックＤＡＣのチップ断面構造図である。
１２・・・・・・半導体基板、１３・・・・・半導体素
子、１４・・・・・・Ｓ １０２膜、１６・・・・・薄
膜抵抗素子、１６・・・・・・Ａ２配線、１７−・・・
・・Ｎ型エピタキシャル層、１８・・・・・・Ｎ Ｓ
Ｇ パッシベーション膜、１９・・・・・・ＰＳＧパッ
シベーション膜、２ｏ・・・・・・ＮＳＧパッシベーシ
ョン膜。Figure 1 shows a monolithic DA using a conventional thin film resistor circuit.
FIG. 2 is a cross-sectional view of a chip of a monolithic DAC using an embodiment of the present invention. 12...Semiconductor substrate, 13...Semiconductor element, 14...S102 film, 16...Thin film resistance element, 16...A2 wiring, 17-...
...N-type epitaxial layer, 18...N S
G passivation film, 19...PSG passivation film, 2o...NSG passivation film.
Claims (1)
子を覆うごとくノンドープドシリケートガラス（ＮＳＧ
）膜と燐シリケートガラス（ＰＳＧ）膜とノンドープド
シリケートガラス（ＮＳＧ）膜とをこの順序に堆積して
なる半導体装置。Non-doped silicate glass (NSG) is placed on the thin film resistive element formed on the substrate to cover the thin film resistive element.
) film, a phosphorous silicate glass (PSG) film, and a non-doped silicate glass (NSG) film are deposited in this order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13830484A JPS6116562A (en) | 1984-07-03 | 1984-07-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13830484A JPS6116562A (en) | 1984-07-03 | 1984-07-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6116562A true JPS6116562A (en) | 1986-01-24 |
Family
ID=15218743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13830484A Pending JPS6116562A (en) | 1984-07-03 | 1984-07-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6116562A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0642167A3 (en) * | 1993-08-05 | 1995-06-28 | Matsushita Electronics Corp | Semiconductor device having capacitor and manufacturing method thereof. |
| EP0673069A2 (en) * | 1994-03-18 | 1995-09-20 | Seiko Instruments Inc. | Insulated gate semiconductor device and method for fabricating the same |
-
1984
- 1984-07-03 JP JP13830484A patent/JPS6116562A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0642167A3 (en) * | 1993-08-05 | 1995-06-28 | Matsushita Electronics Corp | Semiconductor device having capacitor and manufacturing method thereof. |
| US5624864A (en) * | 1993-08-05 | 1997-04-29 | Matsushita Electronics Corporation | Semiconductor device having capacitor and manufacturing method thereof |
| EP0739037A3 (en) * | 1993-08-05 | 1998-04-29 | Matsushita Electronics Corporation | Semiconductor device having capacitor and manufacturing method thereof |
| US6015987A (en) * | 1993-08-05 | 2000-01-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having capacitor exhibiting improved mositure resistance and manufacturing method thereof |
| US6107657A (en) * | 1993-08-05 | 2000-08-22 | Matsushita Electronics Corporation | Semiconductor device having capacitor and manufacturing method thereof |
| US6169304B1 (en) | 1993-08-05 | 2001-01-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having a passivation layer which minimizes diffusion of hydrogen into a dielectric layer |
| US6294438B1 (en) | 1993-08-05 | 2001-09-25 | Matsushita Electronics Corporation | Semiconductor device having capacitor and manufacturing method thereof |
| US6333528B1 (en) | 1993-08-05 | 2001-12-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having a capacitor exhibiting improved moisture resistance |
| EP0673069A2 (en) * | 1994-03-18 | 1995-09-20 | Seiko Instruments Inc. | Insulated gate semiconductor device and method for fabricating the same |
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