JPS61296721A - Fine processing of single crystal silicon - Google Patents

Fine processing of single crystal silicon

Info

Publication number
JPS61296721A
JPS61296721A JP13792485A JP13792485A JPS61296721A JP S61296721 A JPS61296721 A JP S61296721A JP 13792485 A JP13792485 A JP 13792485A JP 13792485 A JP13792485 A JP 13792485A JP S61296721 A JPS61296721 A JP S61296721A
Authority
JP
Japan
Prior art keywords
substrate
oxide film
single crystal
laser beam
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13792485A
Other languages
Japanese (ja)
Inventor
Tsunetoshi Arikado
経敏 有門
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13792485A priority Critical patent/JPS61296721A/en
Publication of JPS61296721A publication Critical patent/JPS61296721A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To give roundness to an angular upper corner edge produced by vertical etching of an Si substrate by applying a laser beam of visible ray range or ultraviolet ray range to the Si substrate after vertical etching. CONSTITUTION:A thermal oxide film 5 is formed on P-type (100) Si substrate 4. Then a pattern is formed with a positive type photoresist 6 and the thermal oxide film 5 is subjected to oriented etching by using the photoresist 6 as a mask. After the resist 6 is removed, the single crystal Si substrate 4 is etched and dipped into a buffer fluoric acid solution and the thermal oxide film 5 is removed and then an ArF excimer laser beam is applied. With this process, the Si surface layer is melted and an angular upper corner edge can be rounded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、単結晶シリコンの微細加工方法の改良に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a method for microfabrication of single crystal silicon.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体集積回路の高集積化は、依然として2年で4倍の
速度で進んでおり、設計寸法もいよいよりブミクロン領
域に突入しようとしている。
The integration of semiconductor integrated circuits is still increasing at a rate of four times every two years, and design dimensions are about to enter the bumikron range.

メモリセルが1トランジスタ1キヤパシターで構成され
、キャパシタのチャージの有無で1ビツトの記憶を行な
うダイナミックメモリの場合、安定した動作を行ないか
つソフトエラーを抑制するため(−は、キャパシターが
30〜5 QFF  である必要がある。パターン寸法
が小さくなる一方で上記容量を確保するためには、ゲー
ト酸化膜を薄くする必要がある。しかしゲート酸化膜の
薄膜化にも限度があるところから、St基板を深く堀り
、縦型にキャパシタをつく9つ?する、いわゆる溝堀リ
キャパシタが提案されている。これは、第2図(;示す
ようにst基板1を垂直1:エツチングした後酸化しで
、底面と側面にゲート酸化膜2を形成し、次(:多結晶
Si3を埋め込んで電極を構成するものである。
In the case of dynamic memory, where the memory cell is composed of one transistor and one capacitor, and stores one bit depending on whether or not the capacitor is charged, in order to perform stable operation and suppress soft errors (- indicates that the capacitor is 30 to 5 QFF). In order to secure the above capacitance while pattern dimensions become smaller, it is necessary to make the gate oxide film thinner. However, there is a limit to the thinning of the gate oxide film, so St substrates are A so-called trench-horizontal recapacitor has been proposed in which capacitors are formed vertically by deep trenching. , a gate oxide film 2 is formed on the bottom and side surfaces, and then polycrystalline Si 3 is buried to form an electrode.

しかしながら、単結晶Siを反応性イオンエツチングで
加工した場合、上端部と下端部は、第2図にも見られる
ように角ばった形となる。これらの角ばった部分では、
ストレスが集中するため酸化膜質が悪く、キャパシター
を構成した場合リークの原因となる。このリークは、メ
モリセルにおいては、記憶保持不良につながる大問題で
ある。リークを防止するためには、角ばった部分に丸み
をつける必要があるが、従来上端部1:丸味をつける方
法がなかった。
However, when monocrystalline Si is processed by reactive ion etching, the upper and lower ends become angular, as can be seen in FIG. In these angular parts,
Due to the concentration of stress, the quality of the oxide film is poor and can cause leaks when used as a capacitor. This leakage is a major problem in memory cells, leading to poor memory retention. In order to prevent leakage, it is necessary to round the angular portions, but conventionally there has been no method for rounding the upper end portion 1.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、垂直エツチングを行なった後、角ばっ
た上端部に丸味をつける方法を提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for rounding an angular top edge after vertical etching.

〔発明の概要〕 本発明は、Si基板の垂直エツチングを行なった後、s
t基板に可視または紫外領域のレーザ光を照射すること
を特徴とする。
[Summary of the Invention] The present invention provides that after vertical etching of a Si substrate, s
It is characterized by irradiating the t-substrate with laser light in the visible or ultraviolet region.

〔発明の効果〕〔Effect of the invention〕

本発明によればSi基板はレーザ光を吸収し、ごく短時
間に溶融し再結晶するために、上端部の角ばった部分が
丸味を帯びる。
According to the present invention, the Si substrate absorbs laser light and melts and recrystallizes in a very short time, so that the angular portion of the upper end becomes rounded.

〔発明の実施例〕[Embodiments of the invention]

以下(一本発明の一実施例を第1図を用いて説明する。 An embodiment of the present invention will be described below with reference to FIG.

まずP型(ioo)si基板4を950℃水素燃焼酸化
することにより850OAの熱酸化M5を形成する。
First, a P-type (IOO) Si substrate 4 is subjected to hydrogen combustion oxidation at 950° C. to form a thermally oxidized M5 of 850 OA.

次f:ボジ型フォトレジスト6を用いてパターン形成を
行ない、このレジストをマスクとして前記熱酸化膜5の
方向性エツチングを行なう。熱酸化膜5のエツチングは
、通常の陰極結合型反応性イオンエツチング装置を用い
、ガスとしてCHF、を用いて行なった(第1図(a)
)。その後O,プラズマ灰化装置を用いてレジスト6を
除去した。次にやはり陰極結合型反応性イオンエツチン
グ装置内に該基板を入れ、CBrFl ガスを導入し、
、圧力0.04Torr rf電力600Wで単結晶8
i基板4のエツチングを行なつた(第2図(b)。
Next f: A pattern is formed using a positive photoresist 6, and the thermal oxide film 5 is directionally etched using this resist as a mask. Etching of the thermal oxide film 5 was carried out using an ordinary cathode-coupled reactive ion etching device using CHF as the gas (see Fig. 1(a)).
). Thereafter, the resist 6 was removed using a plasma ashing device. Next, the substrate was placed in a cathode-coupled reactive ion etching device, and CBrFl gas was introduced.
, single crystal 8 at pressure 0.04 Torr RF power 600W
The i-substrate 4 was etched (FIG. 2(b)).

次に、該Si基板4を緩衝フッ酸溶液中に浸漬し、熱酸
化膜5をはくすした後、人rFエキシマレーザー光を照
射した。ArFエキシマレーザ光は、波長193nmで
パルス巾約10口SeCのパルスレーザ−で、1パルス
当りのエネルギー0.IJ/Jをレンズで5 wit”
角j二集光し1エリアに20パルスずつ照射した。これ
C二より、Si表層がメルトし、第2図(C)のごとく
上端部の角が丸くなる。
Next, the Si substrate 4 was immersed in a buffered hydrofluoric acid solution to remove the thermal oxide film 5, and then irradiated with human rF excimer laser light. The ArF excimer laser light is a pulse laser with a wavelength of 193 nm and a pulse width of approximately 10 SeC, and the energy per pulse is 0. IJ/J with lens 5 wit”
The light was focused at angle j2 and irradiated with 20 pulses per area. At C2, the Si surface layer melts and the upper corner becomes rounded as shown in FIG. 2(C).

ついで、酸化前処理を行ない、950℃ドライot中で
ゲート酸化膜7を形成しく膜厚200A)、さら:=気
相成長法1:より多結晶Si8を形成する。ついで、P
oC/2雰囲気下1000℃で10分間リン・拡散を行
なった後、緩衝フッ酸溶液中に該基板4を浸し、リン拡
散中に多結晶Si8表面(−形成された酸化膜のハクリ
を行々つた。次にポジ型フォトレジストを塗布し、ゲー
ト電極のパターニングを行ない、CF410.混合ガス
プラズマを用いて多結晶Si8のエツチングを行なった
(第2図(d))。
Next, a pre-oxidation treatment is performed to form a gate oxide film 7 in a dry oven at 950° C. (film thickness 200 Å), and then polycrystalline Si 8 is formed by vapor phase growth method 1. Then, P
After performing phosphorus diffusion for 10 minutes at 1000°C in an oC/2 atmosphere, the substrate 4 was immersed in a buffered hydrofluoric acid solution, and the oxide film formed on the polycrystalline Si8 surface (-) was removed during the phosphorus diffusion. Next, a positive photoresist was applied, a gate electrode was patterned, and polycrystalline Si8 was etched using CF410 mixed gas plasma (FIG. 2(d)).

第3図は、このよ51=して形成した溝堀リキャパシタ
ーの電流−電圧−特性を示す図である。明らかにスパッ
タリング作用によって上端の角をとった基板の方が電流
値が小さく、リークがないことがわかる。
FIG. 3 is a diagram showing the current-voltage characteristics of the Mizohori recapacitor thus formed. It is clear that the current value is smaller for the substrate whose upper end is rounded due to the sputtering action, and there is no leakage.

本実施例(;おいては、Mを用いてスパッタリングを行
なったが、M以外でもSiに対して不活性なガスであれ
ば、同様の効果は起こることはいうまでもない。
In this embodiment, sputtering was performed using M, but it goes without saying that a similar effect can be produced using any gas other than M, provided that it is inert to Si.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例として溝堀リキャパシタ形
成過程を示す工程図、第2図は、溝堀りキャパシタの断
面を示す図、第3図は、電流−電圧特性を示す図である
。 1・・・Si基板     2・・・ゲート酸化膜3・
・・多結晶St電極  4・・・Si基板5・・・熱酸
化膜      6・・・ポジ型フォトレジストア・・
・ゲート酸化膜  8・・・多結晶Si電極(7317
)  弁理士  則 近 憲 佑 (ほか1名)第2図
FIG. 1 is a process diagram showing the process of forming a Mizohori capacitor as an embodiment of the present invention, FIG. 2 is a diagram showing a cross section of the Mizohori capacitor, and FIG. 3 is a diagram showing current-voltage characteristics. It is. 1...Si substrate 2...Gate oxide film 3.
...Polycrystalline St electrode 4...Si substrate 5...Thermal oxide film 6...Positive photoresist...
・Gate oxide film 8... Polycrystalline Si electrode (7317
) Patent Attorney Kensuke Chika (and 1 other person) Figure 2

Claims (3)

【特許請求の範囲】[Claims] (1)シリコン基板上に第1の薄膜と感光剤の薄膜とを
順次堆積する工程と、リソグラフィ工程により前記感光
剤薄膜にパターンを焼き付け現像して前記感光剤のパタ
ーンを形成する工程と、該パターンをマスクとして前記
第1の薄膜のエッチングを行ない、続いて前記第1の薄
膜をマスクとして前記シリコン基板の方向性エッチング
を行なう工程と、前記第1の薄膜を除去した後該シリコ
ン基板にレーザ光を照射する工程を具備することを特徴
とする単結晶シリコンの微細加工方法。
(1) a step of sequentially depositing a first thin film and a thin film of a photosensitive agent on a silicon substrate; a step of printing and developing a pattern on the thin film of the photosensitive agent using a lithography process to form a pattern of the photosensitive agent; etching the first thin film using the pattern as a mask; then directional etching the silicon substrate using the first thin film as a mask; and after removing the first thin film, applying a laser beam to the silicon substrate. A method for microfabrication of single crystal silicon, comprising a step of irradiating light.
(2)前記レーザ光が可視および紫外領域の波長を有す
ることを特徴とする特許請求の範囲第1項記載の単結晶
シリコンの微細加工方法。
(2) The method for microfabrication of single crystal silicon according to claim 1, wherein the laser beam has a wavelength in the visible and ultraviolet regions.
(3)前記レーザ光を照射する工程が超高真空下で行な
われることを特徴とする特許請求の範囲第1項記載の単
結晶シリコンの微細加工方法。
(3) The method for microfabrication of single-crystal silicon according to claim 1, wherein the step of irradiating the laser beam is performed under an ultra-high vacuum.
JP13792485A 1985-06-26 1985-06-26 Fine processing of single crystal silicon Pending JPS61296721A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13792485A JPS61296721A (en) 1985-06-26 1985-06-26 Fine processing of single crystal silicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13792485A JPS61296721A (en) 1985-06-26 1985-06-26 Fine processing of single crystal silicon

Publications (1)

Publication Number Publication Date
JPS61296721A true JPS61296721A (en) 1986-12-27

Family

ID=15209864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13792485A Pending JPS61296721A (en) 1985-06-26 1985-06-26 Fine processing of single crystal silicon

Country Status (1)

Country Link
JP (1) JPS61296721A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01216538A (en) * 1988-02-24 1989-08-30 Toshiba Corp Semiconductor device and manufacture thereof
JP2012089735A (en) * 2010-10-21 2012-05-10 Fuji Electric Co Ltd Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01216538A (en) * 1988-02-24 1989-08-30 Toshiba Corp Semiconductor device and manufacture thereof
JP2012089735A (en) * 2010-10-21 2012-05-10 Fuji Electric Co Ltd Semiconductor device and method of manufacturing the same

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