JPS61296471A - Vector processor - Google Patents

Abstract

PURPOSE:To access listed data rapidly and to attain the processing of the listed data at high speed by providing a logic circuit constituted of the combinations of shifters, a validity formation logic part, a selector, a comparator, etc. CONSTITUTION:When the address of the 1st element of the listed data is set up in a register 1 from a scalar processor, the address is set up in a register 5 through the selector 2, a main storage 3, the validity formation logic part 4, etc. Then, a data field is extracted through a shifter 7, and set up in a register 8 and an address field is extracted through the logic circuit 10 constituted of the combinations of shifters and set up in a register 11. The data and address are sent to a vector register through the selector 2, the logic part 4, buses 22, 23, etc. and vector length is stored in a register 14 on the basis of a suppression signal outputted from a comparing circuit 12. Then, pattern matching is executed by a vector arithmetic unit on the basis of the vector length. Thus, the listed data can be processed at the high speed.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a vector processing device, and particularly a method for realizing high-speed access to data having a list structure.[Background of the Invention] Today, data having a list structure is used. is a relational de-
It is widely used in databases, formula processing systems, etc. Figure 3 shows the main memory (MM) of data with a list structure.
This shows the storage format above.

Each element consists of a data field and an address field (list field), and the address field indicates the storage location of the next element. Note that a value indicating the end of the list data (hereinafter, this value will be referred to as "nil") is set in the address field of the final element.

To speed up the processing of data with such a list structure, the main memory is accessed at high speed, the data part excluding the list field is stored in the register of the processing device, and the data is processed again. It is necessary to add a list field to the section and write it to main memory. In order to speed up this series of processing, data address generation 1. It is necessary to perform as much pipeline control as possible to speed up processing such as memory requests and editing data loaded from main memory.

In the past, vector processing devices have been proposed that can process large matrix calculations at high speed (Richard M. Russell)
The CRA'Y-1 computer system (1 Nikkei McGraw-Hill P, 283-295, 1982) does not have a mechanism for processing list-structured data in a pipeline.

[Purpose of the invention]

The object of the present invention is to provide a vector processing device.

The purpose of this invention is to realize high-speed access to list-structured data and speed up data processing based on the list structure.

[Summary of the invention]

In the present invention, the main memory access section of the vector processing device is constituted by logical units such as an address calculation logic section, a load data editing section, and a store data editing section.

In the case of load processing, the at1nos calculation logic unit generates the address of the first element of the list structure data. The main memory is read based on the address, and the data field and the address field of the next element are separated in the load data editing section. This separated data field is sent to a first vector register, and the address field is sent to a second vector register different from the data field and at the same time sent to the address calculation section. In this way, in the processing of the second element and subsequent elements, the value of the address field separated by the load data editing section is used as the address. Ato 1
The value of the Nos field indicates the end of the list data (n
When il) is reached, the length of the list-structured data is determined, so this value is transferred to the vector length register, and the loading process is completed.

In the case of store processing, the address data and calculation data are read from the two registers, and the store data editing section stores the address of the j-th element of the list structure data in the register, and then the calculation data of the j element is stored. nij
In the case of the 6 final element, in which the address of the -1-1 element is added and the edit data is stored at the location in the main memory indicated by the address of the 7j element, "nil" is written in the address field.

By performing the above processing, list-structured data access is speeded up, and data processing is performed in parallel by chaining control via vector registers.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a main memory reference logical unit (load requester) for reading list structure data of a vector processing device;
FIG. 2 also shows a main memory write logic unit l- (store requester) for writing list structure data of the vector processing device.

First, the loading process of list structure data will be explained with reference to FIG. When the vector processing device is activated, the address of the first element of the list structure data is set in register 1 by the scalar processing device. Next, this address is selector 2
The data is sent to main memory 3 via . At this time, a valid signal indicating that the address has been sent from the valid generation logic unit 4 via the path 20 is sent to the main memory 3.

Data read from main memory 3 is stored in register 5. An instruction signal for transmitting data to the register 5 is sent from the main memory 3 via the path 21 every time data is read. Further, the instruction signal increments the contents of the counter 6, which is reset to 1 when the vector processing device is started, by 1.

The data read from the main memory 3 is transferred to the register 5, the data field is taken out by the shifter 7, and transferred to the register 8 to the cell 1, and then passed through the path 22 to the vector register (not shown). ). The number of bits to be shifted by the shifter 7 is set in the register 9 by the scalar processing device when the vector processing device is activated.

On the other hand, the address field of the data read from the main memory 3 is extracted by a logic circuit 10 consisting of a combination of shifters and set in a register 11. This At1nos field is sent to the vector register through the path 234 at the next timing. At the same time, the address field set in register 11 becomes an input to selector 2 and is sent to main memory 3. That is, immediately after sending the first element address of the list structure to the main memory 3, the SE! The valid generation logic unit 4 controls the node 2 to select the path 23 side.

Thereafter, the main memory 3 is referenced using the at1nos sent via the path 23, and by repeating the above operation, the data and address are transferred via the paths 22 and 23.
．． / written to the register.

If the address field of the data read from the main memory 3 has the same pattern as "nil"' in the register 13, the comparison port j! 3.12 sends an inhibit signal on path 24 (
12, the operations of the counter 6 and the valid generation logic unit 4 are interrupted. When the vector processing device is started, the ``nil'' mark is placed in the register 13 by the scalar processing device. When the counter 6 stops, the data length of the list structure data, that is, the vector length is stored in the register 14. .

Hereinafter, vector processing is executed using the vector length on the register 14, but the control of this processing is not directly related to the present invention and will therefore be omitted.

Next, with reference to FIG. 2, the process of configuring the list 1 structure data and writing it into the main memory will be explained. When the list structure data store processing is started, the scalar processing unit stores the at1nos of the first element in the main memory in the 1no register 1, and the bit position indicating the boundary between the data and the at1nos is 1. It is assumed that J·[, is stored in the nozzle 9.

Upon completion of vector processing, data and addresses are set in 1-no registers 52 and 53 via paths 50+51, respectively. The data is shifted by shifter 54;
It is stored in the upper part of the register 55. The subdivision of register 55 is determined by the value of register 9. On the other hand, the address is stored in the lower part of the register 55 via the first node 57. At1/of the first element of list data
The address is stored in register 1, and this address is sent to main memory 3 via register 56 for di-noise. In synchronization with this address transmission, the list 1 of register 55 is
- Data is also sent to main memory 3.

Immediately after the address of the first element is sent to register 1 to 56, selector 60 combines paths 61 and 62. This switching process is performed by control circuit 59 using a valid signal sent from the vector register via path 58. The data of the first element is transferred to the register 55 and the address is transferred to the register 56, and then the data and address of the second element are transferred to 52.53. At the time the data and address of this second element are stored in register 55.

The write at 1nos is from register 53 to register 5.
6, and register 5 is synchronized with this address.
The second element list data of No. 5 is sent to the main memory 3. Thereafter, the same process is repeated.

When the final element of the vector is sent from the vector register via the path 58, the control circuit 59 activates the selector 57, pre-stored in the register 63.
control so that a "nil" button is inserted into the lower part of the register 55.

〔Effect of the invention〕

According to the present invention, it becomes possible to process data having a list structure with a vector processing device, and the scope of application of backup processing is expanded. For example, if you want to check whether a certain pattern exists in list-structured data, the load requester adopting the present invention can load the data from memory After loading the data into the back register and determining the vector processing length, the data is read using the chaining function of the back register and pattern matching is performed by the vector arithmetic unit, resulting in faster processing than conventional scalar processing. The desired processing can be performed. In addition, by using the list requester of the present invention that employs control to generate a list structure and write it to main memory, vector processing can also be used to replace a specific pattern in list structure data and make it invalid data. It can be done at high speed by

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a main memory reference logic unit for reading list structure data of a vector processing device, and FIG. 2 is a diagram showing an example of a main memory write logic unit for writing list structure data. FIG. 3 shows a storage format of list structure data. 3...Main memory, 5...Data register. 7... Shifter, 10... Logic circuit, 54...
・Shifter, 55...Data register. Representative patent attorney Katsoo Ogawa Figure 1 Figure 2 M space

Claims (1)

[Claims] (1) In a vector processing device consisting of a main memory, a plurality of vector registers, a vector arithmetic unit, etc.
In order to access list structure data where each element consists of a data part and an address part indicating the storage location of the next element,
a first control means that separates the list structure data read from the main memory into a data part and an address part and sends them to the vector register, and sends the address part to the main memory as a read address of the list structure data of the next element; A second control that combines the data part and the address part held in the register, converts it into list structure data, writes it to the main memory, and sends the address part to the main memory as a write address of the list structure data of the next element. A vector processing device characterized by comprising: means.