JPS61295597A - Graphic display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a graphic display device for loading image data -iF into an image memory.

[Conventional technology]

FIG. 2 is a block connection diagram showing a conventional graphic display device, in which 1 is a CPU (central processing unit) that controls the entire graphic display device;
2 is a data register that temporarily stores data in the bit depth direction to be written; 3 is a plane selection register that temporarily stores memory plane selection data; 4 is a memory controller; and 5 is an image memory, which includes a plurality of memory planes 5a. ~5n stacked in the depth direction.

Next, we will discuss the operation.

When the CPU 1 writes to the image memory 5, which of the memory planes 58 to 5n does the writing write to?
Input the data to the plane selection register 3,
Latch this. Next, for writing, the CPU 1 calculates data in the depth direction of 9 bits per row, and latches it into the data register 2. After that, the CPUI calculates the addresses on the memory planes 5a to 5n of the image memory 5,
This result is sent to memory 5. At the same time, the memory controller 4 outputs the write signal WE, and by logically ORing it with the data in the plane selection register 3, the write enable signal NE is output only to the specified memory plane surface, and the data in the data register 2 is written.

[Problem that the invention seeks to solve]

Conventional graphic display devices are configured as described above, so that data in the bit length direction, that is, in the horizontal direction; iFt! ! There were problems such as it took time to draw dots in the depth direction, fill in the dots in the horizontal direction, and draw patterns.

This invention was made to solve the above-mentioned problems, and provides a graphic display that can write not only data in the depth direction of one dot, but also data in the horizontal direction of a set bit length in the image memory. The purpose is to obtain equipment.

[Means for solving problems]

The graphic display IT according to the present invention is provided with a plane selection register and a bit selection register, thereby making it possible to write data in the depth direction of one image memory and to write data in the horizontal direction for each memory plane. It is something.

[Effect]

The plane selection register in this invention sets the memory plane to be written to in the image memory after selecting the mode in the depth direction by the mode register and validating the data in the depth direction by the multiplexer. It selects only the memory plane specified by the CAS signal and stores data in the depth direction, and also specifies arbitrary bits using the write enable signal of a specific bit address specified by the bit selection register based on the bit address. Go.

As a result, data in the depth direction of an arbitrary dot can be drawn on a specified memory plane.

On the other hand, after setting the mode register to the horizontal mode and thereby switching the multiplexer to enable horizontal data, the plane selection register is set to which memory plane the CPU writes to. C.P.
When sending a memory address, U sends out the RAS/CAS signal and write enable signal from the memory controller, outputs the RAS/CAS signal only to the specified memory plane via the plane selection register, and sends the write enable signal to the bit selection register. Output to all memory planes via. This allows data in the horizontal data register to be drawn only on a specific memory plane.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. @1
In the figure VC$-, 1 is the CPU, 2 is a data register that temporarily stores data in the bit depth direction to be written, and 3
A is the plane selection register, 4 is the memory controller,
5 is an image memory having n memory planes 58 to 5n. Moreover, each of the memory planes 5a to 5n is m
It has bit length horizontal data. 6 is m in the horizontal direction
A bit data register, γ is a multiplexer as a switching circuit for switching between the horizontal direction and the depth direction, 8 is a mode register for specifying the mode of horizontal drawing or depth direction drawing, and 9 is an m-bit length This is a bit selection register that specifies any bit in the register.

Next, the operation will be specifically explained.

First, writing in the depth direction of the image memory 5 will be explained. In this case, the mode register 8 specifies the mode in the depth direction. As a result, the multiplexer 7 is switched to enable data in the depth direction. Next, which of the memory planes 5a to 5n of the image memory 5 is to be written is set in the plane selection register 3A, and the CPU 1 calculates the data and address to be written. The calculated write data and address are temporarily stored in the depth direction data register 2.

Next, CPtJ 1 divides the address into a memory address and a bit address, and sets the bit address in the bit selection register 9 via the memory controller 4. In addition, by sending the memory address from cPUl, RAS/CA is sent to the memory controller 4.
S signal and write enable signal (hereinafter referred to as WE scratch signal) are output. Therefore, instead of the input signal of the WE-multiplied signal bit selection register 9, the WE-multiplied signal of the bit address specified here is output. Also, RAS/
The CAS signal becomes an input to the plane selection register, which outputs the RAS/CAS signal only to the specified memory plane. Therefore, data of one dot in the depth direction can be arbitrarily drawn in the image memory 5.

Next, writing in the horizontal direction of the one-image memory 5 will be explained.

First, the CPU 1 sets the mode register 8 to the horizontal mode. In response to this signal, the multiplexer 7 is switched to enable the data in the horizontal direction, and the bit selection register 9 is also switched to output the WE times signal to all m-bit portions.

Next, the CPU 1 selects which memory plane is to be written into, sets the selected memory plane in the plane selection register 3A, and then performs arithmetic operations on the memory address and memory data. The data resulting from this calculation is latched in the horizontal data register 6, and the CPU 1 outputs a signal to the memory controller at the same time as sending out the memory address, thereby causing the RAS/CAS signal and the WE multiplication signal to be sent out.

In this case, all the WE times signals are memory play y
However, since the RAS/CA and S signals are output only to a specific memory plane designated via the plane selection register 3Af, the signal is output only to one of the specific memory planes 5a to 5n. , the data in the horizontal data register 6 will be written.

In this way, the identified memory brains 53 to 5n
You can draw data in the horizontal direction on either side.

〔Effect of the invention〕

As described above, according to the present invention, a plane selection register and a bit selection register are provided that select depth direction data or horizontal direction data and supply them to the memory plane, and the memory controller outputs the plane selection register and the bit selection register.
Since it is configured to be controlled by the S/CAS signal and the WE multiplication signal, image data can be freely written in the horizontal and depth directions of one image memory, and from one dot drawing in the depth direction to the horizontal direction. This has the effect of speeding up filling and pattern drawing.

[Brief explanation of drawings]

Figure 1 shows a graphic display device according to an embodiment of this invention, and Figure 2 shows a conventional graphic display device.
FIG. 2 is a diagram showing a display device. 1 is a CPU, 2 is a data register 53 is a plane selection register, 5 is an image memory, 5a to 5''n are memory brains, γ is a multiplexer, 8 is a mode register, and 9 is a bit selection register. Note that the same reference numerals are used in the figure. indicates the same or equivalent part. Patent applicant Mitsubishi Electric Corporation agent Patent attorney 1) Hiroshi Sawa 1:
(2 others) Written amendment of procedure (voluntary)

Claims (1)

[Claims] In a graphic display device in which image data can be arbitrarily written to a plurality of memory planes of an image memory, data is written in the depth direction of the image memory and data is written in the lateral direction for each of the memory planes. What is claimed is: 1. A graphic display device comprising a plane selection register and a bit selection register.