JPS61294547A - Firmware load system - Google Patents

Abstract

PURPOSE:To shorten the leading time of a device by monitoring the overall firmware load request state of the device and changing the address of a normal operation mode into a corresponding address in a loading mode to secure the correspondence between a single address and a single firmware. CONSTITUTION:The firmware given from a master firmware load executing part 100 and plural slave processor data are received by a transfer executing part 200. In this case, a load request state detecting part 4 and a load control part 5 are provided to the part 100. While the part 200 is provided with a load request control part 1, a load state detecting part 2, an answer address control part 3 and a data transfer control part 6 respectively. The part 1 sends the load request signal and the requested signal to the detecting parts 4 and 2. The part 2 sets a load address to the part 6. Furthermore the part 5 fetches the firmware corresponding to each firmware type code given from the part 4. Then the part 6 is set again to the address of a normal operation mode after transfer of data.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a firmware loading method, and when there is a request to load the same firmware from multiple processors, it is possible to load the same firmware instead of loading it individually for each processor. , regarding a firmware loading method that loads simultaneously.

[Conventional technology]

Conventional firmware loading methods do not distinguish between the addresses of each processor when loading firmware, when operating, etc.
Because it had a fixed value, firmware was loaded for each address, that is, for each processor.

Therefore, when there are multiple processors requesting loading of the same firmware, each processor is loaded individually.

[Problem that the invention seeks to solve]

In the conventional firmware loading method described above, when loading firmware, the same number of firmwares as the number of load requests are loaded, and when loading the same firmware to multiple processors, it has to be loaded many times to different targets. There is a problem that it takes a long time to start up the multiprocessor device.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned drawbacks, and to provide an I-firmware loading method that can reduce the startup time of a multiprocessor device by performing loading processing only once for the same firmware load request. be.

[Means for solving problems]

The method of the present invention is a firmware loading method for an apparatus including a master processor that supplies firmware and a plurality of slave processors that receive the firmware, wherein each of the slave processors has:
firmware load request means for specifying firmware to be supplied and requesting loading of the specified firmware; and generating a first signal in response to the firmware load request and the supply of a firmware load request completion signal for the entire device. firmware load state detection means for generating a second signal in response to the supply of a firmware load completion signal to the entire device; and a firmware load state corresponding to the designated firmware in response to the supply of the first signal. a response address of the slave processor as the response address of the slave processor, and in response to the supply of the second signal, an address of the slave processor during operation is set as the response address in place of the firmware load address; address setting means; the master processor includes a detection means M2 for detecting that all of the slave processors have completed firmware load requests and generating a firmware load request completion signal; and a detection means for detecting the second detection means. and firmware loading means for loading the firmware corresponding to the firmware loading address set in each of the slave processors in response to the firmware loading, and for issuing a firmware loading completion signal in response to the completion of the firmware loading. .

[Example] 1 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The firmware loading method shown in FIG. 1 includes a master processor firmware load execution section 100 and one or more slave processor data transfer execution sections 200. Master processor firmware load execution unit 10
0 includes a firmware load request state detection section 4 and a firmware load control section 5, and a slave processor data transfer execution section 200 includes a firmware load request control section 1, a firmware load state detection section 2, and a response address system a section 3. and a data transfer control section 6.

A firmware load request signal S that notifies a firmware load request from the firmware load request control unit 1 of each slave processor! is connected to the firmware load request state detection section 4, and in order to send the type code of the firmware to be loaded to the 7 armware load request state detection section 4, the firmware load request control section 1 connects the common data line L! is connected to.

The firmware load state detection unit 2 generates a firmware load request which is an AND signal of the firmware load processing signal S2 from the J firmware load request control unit 1 and the firmware load request signal S6 from the firmware load request control unit 1 of each slave processor. It inputs the raw signal S5 and outputs a firmware load status signal S3 that informs the firmware load status.

The response address control section 3 receives the firmware load state signal S1 and sets a response address in the data transfer control section 6 via the response address data line L4. Further, when the own node processor is requesting a load, the address sent from the firmware load request control section 1 via the firmware load address data line Lt is used as a response address.

The firmware load request state detection unit 4 receives the firmware load request signal 81 and is connected to the firmware load request raw signal Sll, and when it outputs the firmware load start signal S4, the firmware load request state detection unit 4 outputs the firmware load request signal 81 and outputs the firmware load start signal S4. The firmware load control unit 5 via the identification data line L3.
connected to.

The firmware load control unit 5 loads the firmware specified by the firmware identification data line L3 from a firmware storage location (not shown) via the data line Li, and transfers the firmware to an address compatible with the firmware via the common data line L1. When the transfer of all firmware is completed, a firmware load completion signal S7 is sent to the firmware load request state detection unit 4.

The data transfer control unit 6 transfers the data for the address specified by the response address data line L4 to the common data line L1.
The data is taken in via the data line 1-b and stored in a firmware load area (not shown). The common bus B1 is connected to a slave processor data transfer execution unit (not shown) having a similar configuration.

Next, the operation of this embodiment will be explained.

When each slave processor enters a firmware load request state at device startup, each firmware load request control section 1 reports to the firmware load request state detection section 4 of the master processor using a firmware load request signal S1.

The firmware load request state detection unit 4 increments the firmware type code from the firmware load request control unit 1 via the common data line L1 according to the priority order of each slave processor.

Furthermore, each firmware load request control unit 1 sends a firmware load request source signal S6 indicating that the firmware load request has been completed when sending out the firmware identification code is completed, and further sends a firmware load processing in progress signal to the firmware load state detection unit 2. Output S2.

Upon receiving the firmware load processing signal S2, the firmware load state detecting section 2 notifies the response address control section 3 of the firmware load state through the firmware load state signal line 8s from its own slave processor.

When the response address control unit 3 recognizes that its own slave processor is in the process of loading firmware, the response address control unit 3 issues a request from the firmware load request control unit 1.

The address fetched via the firmware load address data line L2 is set as a response address in the data transfer control unit 6 via the response address data line L4.

On the other hand, the firmware load request state detection unit 4 detects that the firmware load request raw signal S5, which is the AND of the firmware load request source signal S, becomes 11' (in FIG. It is detected that the receiver is attached, and the firmware identification data line L1
The identification codes of all the firmware requested by each slave side are sent to the firmware load control unit 5 via.

The firmware load control unit 5 loads each applicable firmware from a firmware storage location (not shown) via the data line Ls based on the code, and loads the corresponding firmware via the common data line Ll to the address corresponding to each firmware. data transfer. The data transfer control unit 6 on each slave side transfers the data from the common data line Ll corresponding to the address set from the response address data line L4 to a firmware load area (not shown) via the data line L6.

When the firmware load control unit 5 detects that all firmware has been loaded, it reports the completion of the firmware load to the firmware load request state detection unit 4 using a firmware load completion signal S7. ,
.

-Firmware load request state detection unit 4 that received the completion report
forces the firmware load request raw signal Sg @O
”, the end of the firmware U-load is reported to each firmware load state detection unit 2.

When the firmware load state detection section 2 detects the end of the firmware load, it notifies the response address control section 3 that the normal operation state has been entered using the firmware load state signal S3. The response address control section 3, which has received the notification of the normal operation state, sets the response address of the data transfer control section 6 from the firmware loading address to the normal operation address. With the above steps, the firmware loading at the time of device startup is completed.

Further, when only a certain slave processor requests firmware loading after the device 1 is started up, the mosquito slave processor notifies the firmware load request using the firmware load request signal Sl, and sends the firmware identification code to the firmware load request state detection unit 4. Upon receiving the firmware load request, the firmware load request state detection unit 4 sets the firmware load request raw signal Sm, which had been forcibly set to 1@0'', free.At this time, the firmware load request completion signal S of each slave processor is as follows. Since it is already “1” at startup, the firmware load request raw signal Sm
becomes ``l'', and each slave recognizes that it has entered firmware loading processing. Firmware load state detection unit 2 receiving firmware load request raw signal S@
If it is in the process of loading the firmware, it instructs the response address control unit 3 to set the firmware load address using the firmware load status signal S3, and if it is not in the process of loading the firmware.
For example, since the firmware load status signal S1 is not generated, the response address control! Address switching at 1ls3 is not performed. The subsequent operation is similar to that at the time of starting up the device.

As explained above, in the 1-piece actual failure example, the same firmware can be loaded by monitoring the firmware load request status of the firmware 11 and switching the response address to the address corresponding to the load 7 armware when the firmware 5 is loaded. Slave processors that require firmware can be loaded at the same time. Therefore, it is possible to avoid loading the same firmware multiple times and shorten the device start-up time.

〔Effect of the invention〕

As explained above, the present invention monitors the firmware load request state of the entire device, and during firmware loading, switches the response address from the address during normal operation to an address corresponding to the firmware to be loaded.
By making addresses that correspond to one slave processor and one address corresponding to one firmware, processing can be performed for multiple devices at the same time, eliminating the need to load the same firmware multiple times and reducing device startup time. This has the effect of being able to shorten the time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Firmware load request control unit, 2.
...Firmware load status detection section, 3...-
...Response address control unit, 4...Firmware load request state detection unit, 5...Firmware load control unit, 6...Data transfer control unit, Sl... ...Firmware load request signal, S
t...Firmware load processing signal, 8s
...Firmware load status signal, S4...
...Firmware load start signal, Sm...
...Firmware load request signal, S@...
・Firmware load request completed signal, 8 signals...
Firmware load end signal, L1°°゛...Common data line, L2...Address data line for firmware load, Lm...Firmware identification data line, L4...Response address data line for,
Mine tyx

Claims (1)

[Scope of Claims] In a firmware loading method for an apparatus including a master processor that supplies firmware and a plurality of slave processors that receive the firmware, each of the slave processors specifies the firmware to be supplied, and firmware load requesting means for requesting loading of specified firmware; generating a first signal in response to the firmware load request and supply of a firmware load request completion signal for the entire device; and loading the firmware to the entire device. firmware load state detection means that generates a second signal in response to the supply of the end signal; and a firmware load state detection means that generates a firmware load address corresponding to the specified firmware in response to the supply of the first signal. response address setting means for setting an address during operation of the slave processor as the response address instead of the firmware load address in response to the supply of the second signal;
The master processor includes second detection means for detecting that all of the slave processors have finished their firmware load requests and generating a firmware load request completion signal; A firmware loading method comprising: firmware loading means for loading firmware corresponding to a firmware loading address set in each processor and generating a firmware loading completion signal in response to firmware loading completion. .