JPS5839307A - Programmable controller - Google Patents

Abstract

PURPOSE:To prevent a controlled system from entering into a dangerous state by providing a fault flag, an other-equipment fault falg, and an exit inhibiting flag in the working memory of each of plural programmable control machines coupled together on parallel link basis. CONSTITUTION:Two programmable control machines #1 and #2 of the same constitution are coupled together through a link bus CB and a fault signal line SB. In the working memory WM8 of each control machine 1, a fault flag F1 to be set when a fault is detected by a battery fault detector 12, a fault falg F2 to be set when a fault is detected by a temperature fault detecting circuit 13, and an other-equipment flag F3 to be set when a fault reception signal has a high level are set. Further, an output inhibiting flag FO to be set or reset in accordance with the result of optional logical arithmetic among the flags F1, F2, and F3, and optional input and output data is set in the memory 8, and thus prescribed output conditions are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable controller, and in particular to a programmable controller that can construct a parallel link type controller system in which a plurality of controllers are connected to each other via a link bus and the entire controller functions as one controller.・
Regarding the controller.

Conventionally, large-scale programmable
whereas I had to use a controller.
A parallel link type programmable controller system was designed to be able to handle large-scale control objects by using a plurality of relatively small-scale programmable controllers. In other words,
Each 11'' grammar pull controller is provided with an input/output memory having a capacity sufficiently larger than the number of input/output terminals f of its own machine.

For example, if one programmable controller has 64 input/output terminals, and a maximum of 4 controllers can be connected as a parallel 9296-type system, each controller's output horn memory stores human output data. The area should have a capacity of at least 64 x 4 bits. When only one programmable controller is used, it operates as a normal controller with 64 input/output points, but when multiple controllers are connected via a link bus, the execution of each other's user programs Each program controller is provided with input/output data exchange means and knee 41 program synchronization execution means so as to exchange data in each other's input/output memories in synchronization with each other. This allows the input/output status to be transmitted to other machines, the input/output status of other machines to be received by the own machine, each user program executed on each machine based on the overall input/output status, and the execution results returned to the machine. It performs control operations that communicate information to each machine.

Therefore, in the system in which four grammar controllers in the above example are linked, the number of input and output ports is 64 x 4.
The same control function as controlling one system of large-scale control objects using 11 programmable controllers can be achieved by sharing and executing the control programs for that system among 4 controllers.

In the case of the parallel link system described above, multiple linked programmable controllers are connected to one block.
] Since there is a device that functions like a Gramapul controller, if one of the multiple linked controllers malfunctions and cannot perform normal control, the controlled device must be stopped unless the υNil operation of the entire system is stopped. may fall into a completely uncontrolled state,
Extremely dangerous.

In addition, conventional programmable controllers have a means for detecting abnormal battery voltage, a means for detecting an abnormal increase in temperature within the device, and a parity check of the pass line within the device to control the data. An abnormality diagnosing means such as a means for detecting an abnormality is provided, and when an abnormality in the device is detected by this abnormality diagnosing means, the operation of the programmable controller is stopped (all output signals are turned off). It was configured.

However, from the user's perspective of a programmable controller, when some kind of abnormality occurs within the device, the operation of the device is completely stopped, regardless of the type of abnormality or the situation of the object to be controlled when the abnormality occurs. In practice, it was often not always appropriate to do so.

This problem becomes even more complicated in the case of parallel link systems, where each programmable controller is fixedly configured to stop its operation when an abnormality is detected. Not appropriate.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to determine what kind of abnormality inside the device is detected, and what kind of situation the $17111 object is in when outputting the control output. In addition to making it possible for the user to freely set whether to inhibit the state and assemble it as part of the program, when the above-mentioned parallel link system programmable controller system is configured, the linked When one of the multiple programmable controllers disables control output due to an abnormality, the abnormal signal is immediately transmitted to the other programmable controllers, and each programmable controller receives the abnormal signal from the other controllers. It is an object of the present invention to provide a programmable controller in which whether or not to inhibit the control output operation of the controller itself can be set as part of the user program.

In order to achieve the above object, the present invention provides a plurality of types of abnormality diagnosing means for detecting abnormalities inside a device, and a plurality of types of abnormality diagnosing means that are set corresponding to each abnormality diagnosing means and set or reset according to the diagnosis results. an abnormality flag, an abnormality signal receiving means for receiving an abnormality signal emitted from another device, another device abnormality flag that is set when the receiving means receives a C abnormality signal, and a user 10g. an output prohibition flag that is set or reset as a result of any logical operation between the abnormality flag, the other machine abnormality flag, and any input/output data by executing a command arbitrarily set as part; Control output operation is prohibited when this output prohibition flag is set.
t and an output inhibiting means for setting the output state to a predetermined output state, "-2
The present invention is characterized in that it includes an abnormality signal transmitting means for transmitting an abnormality signal to other devices when the output prohibition flag is set.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

In FIG. 1, #1 and #2 are programmable controllers according to the present invention, respectively, and connect two programmable controllers with the same configuration to a link bus CB.
FIG. 12 is a diagram configuring the above-mentioned parallel link type controller system by connecting the controller with the abnormal signal line SB. Programmer Controller #1. #2 has a basic configuration including a user program memory (PM) 1 in which a user program is stored, an input circuit (rU) 2 to which an external input signal is applied, and an output circuit (OU) 3 to send out an external output signal. , the input/output memory (IM>4, which serves as a buffer memory for input/output data corresponding to the input circuit 2 and the output circuit 3), and the 1-program memory 1, each of which executes instructions at high speed sequentially. an instruction execution means for performing logical operation processing based on the data in the input/output memory 4 and rewriting the output data of the input/output memory 4 with the result of the processing; This programmable computer has input updating means for writing, and output updating means for setting output data in a predetermined area of the input/output memory 4 to the output circuit 3.
When only one controller is used, it operates in exactly the same way as a conventional programmable controller.

In the programmable controller according to the present invention, in order to construct the above-mentioned parallel link type controller system, two! Logfumable controller #1. A machine number setting device for determining the priority order during input/output data transfer between the link unit (IU) 5 that connects #2 at the (8th line CB and SB) and the two programmable controllers #1 and #2. (In addition to having SL>6,
The capacity of the input/output memory 4 has an area corresponding to the number of terminals of the input circuit 2 and output circuit 3 of the own machine, and an area corresponding to the number of terminals of the input circuit 2 and output circuit 3 of the other machine. . Furthermore, programmable controller #1. #2 is connected via the link bus CB (-), the input/output memory 4 of each other is synchronized with the execution operation of each other's user programs.
The system includes input/output data exchange means for exchanging data, and user program synchronization execution means.

The above-mentioned instruction execution means, input updating means, output history cutting means,
The main signal processing operations of the programmable controller, such as input/output data exchange means and user program synchronization execution means, are performed by a central processing unit (CPLJ) 9-7 comprised of a so-called microprocessor. The CPU 7 uses a working memory (WM) 8 as a temporary storage area for various variable data to perform various processing operations.

Own machine #1. The address space of each input/output memory 4 in #2 is the same, and as shown in Figure 2, which shows the address area division of the input/output memory 4,
11 corresponds to the input circuit 2 of the #1 machine, and areas #11 and #12 correspond to the output circuit 3 of the #1 machine. In particular, #11 is the area where the output data is rewritten by the user program of machine #1, and rear #12 is the area where the output data is rewritten by the user program of machine #1.
This is the area where the output canister is rewritten by the user program of the No. 2 machine. Similarly, #21 is an area corresponding to the input circuit 2 of the #2 machine, and #21 and #22 are areas corresponding to the output circuit 3 of the #2 machine. especially,
#21 is an area where the output data is rewritten by the #1 machine, and #22 is an area where the output data is rewritten by the #2 machine.

The above-mentioned input/output data exchange means is the rear #110 of the input/output camera t4 from the input circuit 2.
11 is transferred to #11 of input/output memory 4 in machine #2, and then in machine #1! Transfer the replaced output data of area #11 of input/output memory 4 to #2 machine #7 #11, transfer the output data of area #12 replaced in #2 machine to #1 @ machine,
The input data read from the input circuit 2 to #21 in the #2 machine is transferred to #21 in the #1 machine, and the output data of #21, which was changed by 1 in the #1 machine, is transferred to the J rear #21 of the #2 machine. , is a control for transferring the output data of #22 rewritten in the #2 machine to the 1-rear #22 in the #1 machine. The order of transfer of these input/output data, the order of input/output update operations in each machine, and the order of user program execution operations will be explained later.

FIG. 3 shows a smaller configuration of the link unit 5 related to the link bus CB and abnormal signal line SB. As shown in FIG. 3, the CPLI 7 is connected to the link bus CB via the μ-path transceiver/receiver (B-R) 9, thereby allowing the above-mentioned input/output data to be exchanged. The abnormal signal line SB consists of an A-Pun collector bus, and own machine #1. The abnormal signal between #2 and #2 is transmitted and received through this single signal line. That is, the output element to which the line SB in the link unit 5 is connected is the A-bun collector transistor 10. Then, when the abnormality signal ST output from the CPLI 7 becomes 1-level and the transistor 10 is driven, the abnormality signal line SB becomes active (L level). Further, an inverter 11 is provided to input the state of the abnormal signal line SB to the CPU 7. When the abnormal signal line SB becomes active (level), the output signal of the inverter 11 (referred to as abnormal reception signal E-8T) becomes 1 level, and the CPU 7 receives the abnormal signal. These structures correspond to the above-described abnormal signal receiving means and abnormal signal transmitting means.

Furthermore, the programmable controller of this embodiment is
As an abnormality detection means for detecting abnormalities inside the device, a single abnormality detection circuit (BC) is used to detect abnormalities in battery voltage.
12, and a temperature abnormality detection circuit (TC) 13 for detecting temperature abnormalities within the device. The outputs of these abnormality detection circuits 12 and 13 are supplied to the CPU 7,
PLI7 [Therefore, it is constantly monitored. Similarly, the other aircraft abnormality signal E-8T mentioned above is also constantly monitored by CPLI7?
It has been J2. The working memory 8 contains an abnormality flag F1 that is set when the battery abnormality detection circuit 12 detects an abnormality, and an abnormality flag F2 that is set when the temperature abnormality detection circuit 13 detects an abnormality.
A "other machine abnormality" flag F3 is set, which is set when the abnormality reception signal E-8T reaches 1 level.Historically, the working memory 8 stores part of the user program during the operation of the above command execution means. By executing a command arbitrarily set in the user program memory 1 as
Furthermore, an output inhibit 1 flag FO is set or relayed as a result of an arbitrary logical sieve with arbitrary input/output data.

Further, as will be described later, when the output prohibition flag [0 is set, output prohibition means is provided which prohibits the operation of the output update means described in 1 and sets the output state to a predetermined output state.

The output prohibition flag FO is set to each flag F1. F2. For example, in the case of a programmable controller using a ladder diagram method, as shown in FIG. The prohibition flag [0 is set as the output relay, and each flag Fl, F=2. F3 is treated as an input contact, and these input contacts F1. F2゜F
3 and any input/output contacts related to the device to be controlled, converting this into a predetermined command format, and setting it in the user program memory 1 in advance. In the example shown in FIG. 4, when the temperature anomaly flag E2 is set, the output prohibition flag FO is unconditionally set, the other machine abnormality flag F3 is set, and the manual connection is turned on. In this case, the output status 1-nofugu FO is set, and the battery abnormality flag F1 is also set, and when the input contact I2 is turned on, the output prohibition flag F is set.
The user program is designed so that O is set.

Next, the two programmable controllers #1.
The processing procedures performed by both CPUs 7 when #2 constitutes a parallel link type controller system will be explained with reference to the flowchart of FIG. Own machine #1.
When the initial processing is completed in #2, in the first step 101, the input data applied to the input circuit 2 of each own machine is transferred to a predetermined area of the input/output memory 4 (for #1 @ machine - rear #1i, for #2 machine #21).

When this input updating operation is completed, each device notifies the other devices of the completion. In the next step 102, the end of the input update operation is notified from each other device. Both #1. When the input update operation for both #2 is completed, the process proceeds to the next step 103 and 104, and the input/output memory 4 of the #1 machine is updated.
■ Transfer the input data of rear #11 to #2. In the next steps 105 and 106, the input data in area #21 of the input/output memory 4 in machine #2 is transferred to machine #1. From the above, both cases #1. This means that #2 exchanges input data with each other.

Next, each machine #1. Step 107゜108 in #2
Proceeding to Step 2, the user programs stored in each user program memory PM are executed once. As a result, the output data of the occupancy camera E4 is rewritten according to the execution results of each command, and the state of the output prohibition flag FO described above is also determined. Own machine #1. #2 communicates this to the host when the execution of the needs program is completed. Step 109 continues while checking whether each other machine has finished executing the user program.

Own machine #1. When #2 both finishes executing the user programs, the process proceeds to the next steps i1o and ii1, and the output data of areas #11 and #21 in the input/output memory 4 of machine #1 is transferred to machine #2. Then step 112
．． 113, the output data of areas #12 and #22 in the input/output memory 4 of the #2 machine is transferred to the #1 machine.

Now each 111#1. #2 exchanges the rewritten output data with each other by executing their respective user programs.

In the next step 114, it is determined whether the output prohibition flag FO is set or not. The fact that the output prohibition flag FO is reset means that a normal operation is performed without prohibiting the control output, and in this case, the process proceeds to step 115 to perform an output update operation. That is, in the #1 machine, the output data of areas #11 and #12 in the input/output memory 4 is transferred to the output circuit 3. In addition, areas #21 and #22 on #2 @ machine
The output data of is transferred to the output circuit 3. Next step 1
At step 16, the abnormal signal ST is set to 1-level, and the transistor 10 of the link unit 5 is made inactive.

In the next step 119, the output of the battery abnormality detection circuit 17-12 is checked to determine whether there is an abnormality. If it is abnormal, the abnormality flag F1 is hit in step 121, and if it is not abnormal, the abnormality flag F1 is reset in step 120. In the subsequent step 122, the output of the temperature abnormality detection circuit 13 is checked to determine whether there is an abnormality. If it is abnormal, abnormality flag 2 is set in step 124, and if not abnormal, abnormality flag F2 is reset in step 123. In the following step 125, the abnormal reception signal E-8 from the link unit 5 is checked, and it is determined whether this (I'1 No. E-8T is abnormal). If it is abnormal, step 127 sets the other machine abnormality flag F3, and if there is no abnormality, resets the other machine abnormality flag F3 in step 126.In the following step 128, various processes such as monitor display and input reception processing from a program console (not shown) are performed.
8 processing (operating system) is performed, and then returns to step 101, the input update operation.

The above steps 101 to 128 are executed at a repetition rate of -18=speed. Due to the overexecution, the input/output data changes according to the control status signal of the control acid equipment, and both #1. The abnormality flags F11. F2 and other machine abnormality flag F3 change. In the #1 machine, for example, as shown in Fig. 4, the driving conditions for the output prohibition flag FO are set by the user, and in this #1 machine, for example, the input contact ■1 is turned on, and the Abnormal.

If flag F1 is set, then step 107
．． By executing the user program 108, the output prohibition flag FO is set. A, step 114
It is detected that the output prohibition flag FO is set in step 115, and the output update operation in step 115 is not performed, and step 1
In step 117, all external output signals derived from the output circuit 3 are turned off (output is prohibited).

Next, the process proceeds to step 118, where the abnormality signal ST is set to 1 level, the transistor 10 is driven, and the abnormality signal line SD is activated (L level), and the process proceeds to step 119.

On the other hand, since the abnormal signal line SB is activated by the #1 machine, Step 1 is activated on the #2 machine side.
After executing Step 25, it is detected that the abnormality reception signal E-8T is at H level, and the other machine abnormality flag F3 is set. Then, when the user program is executed based on this other machine abnormality flag F3 being set, the output prohibition flag FO in machine #2 is set according to its contents.
will also be set. In other words, it can be arbitrarily set by the user program of the #2 machine that the #2 machine also receives an abnormal signal from the #1 machine and is placed in an output inhibited state.

Although the above embodiment describes an example in which a parallel link system is configured using two programmable controllers, the present invention is not limited to this, and can be implemented using even more programmable controllers. It can be applied in exactly the same way to constructing a parallel link system. In addition, the abnormality diagnosis function of each programmable controller is not limited to the examples mentioned above, but also includes a parity check function of the data bus in the CPU and detection of various abnormalities on other circuits. .

Furthermore, in the above embodiment, all external output signals are turned off as the output prohibition mode, but the present invention is not limited to this, and the output state immediately before the output prohibition flag is set is maintained. Alternatively, it may be configured to output a specific output pattern set in advance.

As explained in detail above, this invention relates to! According to the Logramaple Controller, when a parallel link type controller system is configured with multiple units, what kind of abnormal state is detected in each unit, and what kind of control state is the control output operation of each unit? The right side of the user can set conditions that are appropriate for the use of the entire system as to whether or not to prohibit the output operation. Unlike the prohibition, it does not put the controlled object into a dangerous state, and it can respond to various requests from the user, making it extremely easy to use.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a parallel link type controller system configured using two programmable controllers according to the present invention, and Fig. 2 shows the allocation status of the address 1 rear of the output memory 4 of each machine in the same system. 3 is a diagram showing an example of the circuit of the link unit LU,
FIG. 4 is a diagram showing an example of a threaded bunk room program for inhibiting output, and FIG. 5 is a flowchart showing the processing procedure of each machine constituting the above system. 1...Kneezer program memory 2...
...... Input circuit 3 ...... Output circuit 4 ...... Input/output memory 5 ...... Link unit = 22-7... ......Central processing unit 8...
... Working memory 12 ... Battery abnormality detection circuit 13 ... Temperature abnormality detection circuit FO ... Output prohibition flag Fl, F2 ... Abnormality flag F3. ...Other machine abnormality flag Patent applicant Tateishi Electric Co., Ltd. 23- Figure 2 Figure 3 Figure 411

Claims (1)

[Claims] (1) It has 6 input/output memories, which is sufficiently larger than the number of input/output terminals of its own machine, and when it is connected to another machine via a link bus, the input/output memory of each machine is synchronized with the execution operation of each other's user programs. In a programmable controller equipped with an input/output data exchange means for exchanging data and a coser program synchronization execution means, a plurality of types of abnormality diagnosis means for detecting abnormalities inside the equipment and settings corresponding to each abnormality diagnosis means are provided. A plurality of abnormality flags that are set or reset according to the diagnosis results, an abnormality signal receiving means that receives an abnormality signal emitted from another device, and another device that is set when the receiving means receives an abnormality signal. By executing a command arbitrarily set as part of the abnormality flag and knee ty 70 grams, it is set as a result of any logical sequence between the above abnormality flag, other machine abnormality flag, and any input/output data. or an output prohibition flag to be reset, an output prohibition 1 means for prohibiting the control output operation to achieve a predetermined output state when the output prohibition flag is set, and an output prohibition 1 means for inhibiting other equipment when the output prohibition flag is set A programmable controller comprising: abnormal signal transmitting means for transmitting an abnormal signal.