JPH0247723A - Microprogram controller - Google Patents

Abstract

PURPOSE:To receive a micro code from another processor at the time of trouble of one processor by providing an inter-processor connection circuit for communication between two microprocessors. CONSTITUTION:When power sources of processors 1 and 2 are turned on, a loading indication is sent from a microprocessor 14 to a loader control circuit 12. The loader control circuit 12 receives this indication to load the micro code from a loader 11 and stores it in a control storage circuit 13. When the circuit 12 succeeds in loading, the microprocessor 14 performs the call processing to detect the state of the processor 2. By this processing, the processor informs the other processor of its own state and detects the state of the other processor, and load completion, loading, and failure in loading are informed and detected. First, the state of load completion of the microprocessor 14 is sent from the microprocessor 14 to a processor 24 through an inter-processor connection circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device, and more particularly to a microprogram control device that uses two sets of the same processors and each loads the same microcode at power-on.

[Conventional technology]

Conventionally, this type of microprogram control device has been used to start up two sets of processors, and if one of the loaders or loader control circuits has a fault, the faulty processor is disconnected and the processor is operated as a single processor. I'm trying to get into action.

[Problem to be solved by the invention]

In the above-mentioned conventional method of disconnecting the faulty loader or loader control circuit when one side of the loader or loader control circuit fails, even if the loader or the circuits that make up the processor other than the loader control circuit are normal, However, since the processor is separated, there is a drawback that the processor cannot be operated effectively using a normal circuit.

[Means to solve the problem]

The microprogram control device of the present invention has two sets of processors each including a loader for storing microcode, a loader control circuit for controlling the loader, a control storage circuit for storing microcode, and a microprocessor for executing microinstructions. In the microprogram control device, an interprocessor connection circuit performs communication between the microprocessors of the two sets of processors, and when storing the microcode in the control storage circuit, one microprocessor communicates the storage state of the microcode between the processors. The microcode is transmitted to the other microprocessor via the connection circuit, and if the microcode cannot be stored in one control memory circuit, the microcode is stored from the other microprocessor to the other control memory circuit via the interprocessor connection circuit. and a microprocessor that receives and stores the generated microcode.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which two sets of processors 1 and 2 are connected to each other via a bus through inter-processor connection circuits 3 and 4, respectively.

Processors 1 and 2 are each microprocessor 1
4 and 24 and control storage circuits 13 and 23 . connected to microprocessors 14 and 24, respectively. Loader control circuits 12 and 22 and loaders 11 and 21 connected to the loader control circuits 12 and 22, respectively.
It is composed of. Note that processor 1 is set to have a higher priority than processor 2.

Next, the operation when the power is turned on in the above configuration will be explained with reference to the flowcharts of FIGS. 2(a) and 2(b). When power is applied to processors 1 and 2, in step (2), both processors start operating, but processor 1 will be explained as a representative. An instruction for loading is sent from the microprocessor 14 to the loader control circuit 12 (step 2). In response to this instruction, the loader control circuit 12 loads the microcode from the loader 11 and stores it in the control storage circuit 13 (step 2). Next, it is checked whether the loading was successful (step ■), and if it was successful, the microprocessor 14 performs Ca1l processing to obtain the status of the processor 2 (
Step ■).

This Ca1l process informs the other side of its own status and learns the other side's status: loading complete, loading in progress.

Contains load failure conditions. First, the microprocessor 14 sends its own load completion state to the inter-processor connection circuit 3, and then to the microprocessor 24 through the inter-processor connection circuit 4 of the processor 2 via the inter-processor data bus.

The microprocessor 24 reads the content of the received state and performs the Ack process in response to the Ca1l process. A
The ck process returns its state to the other party, that is, from processor 2 to processor 1. Note that the microprocessor 24 thereafter performs processing according to the state. On the other hand, the microprocessor 14 checks whether the Ack information has been received from the processor 2 (step ■), and if it is sent, checks the contents (step ■), and if the state obtained by the Ack processing of the processor 2 is loading, then , the microprocessor 14 of the process 1 waits for a period of time in step 1, and then performs the Ca11 process again. Processor 2 Ack
If the Z state obtained by the processing indicates that loading has been completed, both processor 1 and processor 2 have been properly loaded and will thereafter operate normally. If the state obtained by the Ack processing of the processor 2 is that the load is unsuccessful, the microprocessor 14 of the processor 1 first checks the number of retries (step 2).

If the number of retries is less than the predetermined number, the microcode is transferred from processor 1 to processor 2 (step 2). For this transfer, first the microprocessor 1
4 reads the stored microcode from the control storage circuit 13 and sends it to the interprocessor connection circuit 3. The interprocessor connection circuit 3 outputs the received microcode to the interprocessor data bus. The inter-processor connection circuit 4 of the processor 2 receives the value on the inter-processor data bus, that is, the microcode, and sends it to the microcode source 24.
send to Microprocessor 24 writes the received microcode into control storage circuit 23.

When the transfer of all the microcodes to be transferred is completed by repeating the above transfer operation, the microprocessor 14 of the processor 1 returns to step (3) again and performs the Ca1l process, and checks the status returned by the Ack process from the processor 2. I'll have to check. If the number of retries exceeds the specified number in step (2), the microprocessor 14 does not access the inter-processor connection circuit 3, disconnects the processor 2 without being successfully loaded, and ends the process. Step again
In step (2), processor 1 performs Ca1l processing, and if processor 2 does not perform Ack processing within a certain period of time, processor 2 is disconnected and the process ends.

Next, when the loading of the processor 1 is not successful in step (2), the processor 1 issues Ca1l including the load failure status (step (2)). This Ca1
l is transferred to processor 2, and processor 2 performs Ack processing in response. processor 1 is processor 2
Check to see if Ack information has been received from processor 2 (step o), and if it is sent, check its contents (step ■).
If the state obtained by the Ack process is loading, the process returns to step (3), waits for a time, and performs the Cal process again. If the state of the processor 2 is completed in step (2), the microprocessor 14 checks the number of retries (step [phase]). When the number of retries is less than the predetermined number, the microcode is transferred from processor 2 to processor 1. This transfer is performed by a request from processor 1 to processor 2, and the method is the same as step (2), but the transfer direction is reversed.

When the transfer is completed, the process returns to step (2) and the operations up to step (2) are performed. Note that if the Ack from processor 2 does not return even after a predetermined period of time has elapsed in step @, both processor 1 and processor 2 terminate as loading failure. Also, when receiving the information that the load was unsuccessful from the processor 2 in step (2), both the processors 1 and 2- terminate the process with the result that the load was unsuccessful. Furthermore, when the number of retries exceeds the predetermined number in step [phase], the loading of the processor 1 is unsuccessful, but the processor 2 completes the loading and enters the operating state.

〔Effect of the invention〕

As explained above, in a system using two identical processors, when the loader and loader control circuit of one processor malfunctions and does not operate normally, the present invention allows microcode to be sent from the other processor. This has the effect of allowing both processors to perform operations from then on.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
and (b) is a flowchart of the microcode storage operation in FIG. 1.2... Processor, 3.4... Inter-processor connection circuit, 11.21... Loader, 12.22... Loader control circuit, 13.23... Control storage circuit, 14°24 ...Microprocessor.

Claims (1)

[Claims] A microprogram control device having two sets of processors each consisting of a loader for storing a microcode, a loader control circuit for controlling the loader, a control memory circuit for storing the microcode, and a microprocessor for executing microinstructions. an inter-processor connection circuit that performs communication between the microprocessors of the processors; and when the microcode is stored in the control storage circuit, the storage state of the microcode is transferred from one microprocessor to the other microprocessor via the inter-processor connection circuit. If the microcode cannot be stored in one control memory circuit, the other microprocessor transfers the microcode stored in the other control memory circuit via the interprocessor connection circuit. 1. A microprogram control device, comprising: a microprocessor for storing information.