JPS62284448A - Initial program loading system - Google Patents

Abstract

PURPOSE:To speed up the rise of system operation by determining whether initial program loading (IPL) from a master station to a slave station is to be executed or not in accordance with the existence of damage of the contents of a main storage device. CONSTITUTION:At the time of turning on the power supply of a system, a CPU 1 reads out the existence of a voltage drop signal 1. When the signal 11 is significant, i.e. the voltage of a battery 10 is <= a set point, the contents of the main storage device 2 are regarded as damaged ones and an IPL request is outputted to a master station device 6 in the master station A to execute IPL from the master station A to the device 2. When the signal 11 is insignificant, i.e. the voltage of the battery 10 is >= the set point, there is no memory damage and the program of the slave station B is left as it is, so that the program is immediately started without outputting the IPL request to the master station A. Thereby, time required for IPL can be omitted and the system operation of a network system can be immediately attained.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] This invention relates to an initial program load method for loading a program transferred from a master station through a data line such as a network system into the main storage device of a slave station. It is related to the method.

[Conventional technology]

FIG. 3 is a block connection diagram showing an outline of the conventional initial program loading method disclosed in, for example, Japanese Patent Publication No. 57-22131. is a slave station, and in slave station B, 1 is a central processing unit i1 (hereinafter referred to as CPIJ), 2 is a main storage device, and 6 is a slave station.
4 is a communication control device; 4 is an initial program loader consisting of a read-only memory in which a program for initial program loading (hereinafter referred to as IPL) is stored; 5;
1 is a data line connecting master station A and slave station Bi, 6 is a master station device, 7 is an external storage device in master station A, and 8 is a program to be IPLed to slave station B.

Further, FIG. 4 is an explanatory diagram showing an example of an IPL procedure between the master station person and the slave station 8. In FIG.

Next, the operation will be explained.

When the CPU 1 is powered on, the initial program loader 4 automatically starts executing the IPL operation. First, C
PU1 uses this execution start program to
Sends IPL request transmission data to. The communication control device 13 transmits its IPL to the main station device 6 through the data line 5t.
Based on this IPL request, the main station device 6 transmits the request.
A program 8 to be loaded into the slave station B stored in the external storage device r117 is searched for, and the searched program is transmitted to the slave station B via the data circuit 5. In the slave station B, the IPL data dl' received through the communication control device 6 is stored in the main storage device 2 by the initial program loader 4. In this way, the IPL data d is sent in order.
2... dn is stored in the main storage device 2 in the same manner, and when all IPL operations are completed, this is transmitted from master station A to slave station B, and the initial of slave station B, which received notification of the completion of 11'L. The program loader 4 finishes executing the load and starts the program in the main storage device 2 that has been received and stored so far. With the above, the IPL work is completed.

[Problem that the invention seeks to solve]

Since the conventional initial program loading method is as described above, even if a program is already stored in the main storage device 2, an IPL request is made to the main station, and therefore, the power is turned on. The start-up of system operations such as the subsequent network is delayed; for example, if there is a large amount of programs to be loaded into slave station B or the transmission speed of the data line is slow, the start-up of the system operations will be delayed. - In order to improve this problem, the initial program is stored in the read-only memory (
It is also possible to store it in ROM (ROM) (in LCJM), but it will be necessary to rewrite the memo V+ each time the program contents are changed, and it is impossible to change the above program from the main station A 11II. There were some problems.

This invention was made to solve the above-mentioned problems, and it enables initial program loading from the master station to the slave station, and also allows the program to be saved in the main memory when the system is powered on. In some cases, the overall purpose is to obtain an initial program loading method that can speed up system operation by allowing the program to be started immediately.

[Means for solving problems]

The initial program loading method according to this invention is as follows:
A batch IJk is provided for memory backup in the main memory of the slave station that stores the program, and if it is determined that the stored contents have been destroyed due to a voltage drop in this battery, the main station will transfer the program to the main memory of the slave station. When the above program is loaded, and the battery voltage has not decreased, the program in the main storage device is started immediately without issuing an IPL request to the main station. . Further, when an error in a program in the main memory is detected, the program can be loaded into the main memory as necessary.

[Effect]

The main memory device of this invention is protected by a memory backup battery even in the event of a momentary power outage or power outage, so as long as the program is stored in the main memory device without being destroyed, the main station To quickly start up system operation by immediately starting the stored program without paying an IPL request fee.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is the CPU of slave station B, 2 is the main storage device, and C is a low-consumption device using MOS memory, 6 is a communication control device, 4 is an initial program loader having an IPL program, 10 11 is a memory backup battery that guarantees the memory contents of the main storage device 12 even in the event of a power outage, and 11 is an output when the voltage of the battery 10 drops (when the battery voltage drops below the voltage that guarantees the memory contents). low battery voltage signal, 12
1 is a parity check circuit that performs a parity check on successive data at the read timing of the main storage device 2 when the CPU 1 executes a program, and 16 is a parity error detection signal.

Note that other parts that are the same as those shown in FIG. 4 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

In addition, the main memory device I2 of the slave station B is generally a CMOS memory with low current consumption as described above, and in order to prevent the memory contents from being destroyed (erased) in the event of a power outage, the memory is powered by a battery 10 such as a lithium battery. A backup is performed. However, if the power outage becomes long, the battery capacity will decrease
voltage gradually decreases. The contents of the main memory device 2 require that a voltage equal to or higher than the guaranteed voltage be supplied to the memory.

Next, the operation will be explained. First, when the system is powered on, the presence or absence of the voltage drop signal 11 of the battery 10 is determined by 1 cPU.
1 reads. If the voltage drop signal 11 is significant, then
In other words, when the voltage of the battery 10 becomes lower than the set value, it is assumed that the contents of the main storage device 2 have been destroyed, and an IPL request is issued to the main station device 6 of the main station A, and the main station A issues a ! ! - Execute. - 10,000, voltage drop signal 11
If it is meaningless, that is, if the voltage of the battery 10 is higher than the above set value, there is no memory corruption and all the programs of slave station B remain in the main memory, so master station A
The program is immediately started without making an IPLi request to the program. Therefore, the time required for IPL is not required, and a system such as a network system can be operated immediately after the power is turned on.

Next, while the CPU 1 is executing the program and reading the program from the main storage device 12, the parity check circuit 12 detects whether the program that is the memory contents has been destroyed, and if a memory parity error is detected. is detected, the memory integrity error detection signal 16
is transmitted to the CPU1, causing a forced interrupt to be generated to the CPU1.

Therefore, as shown in the flowchart of FIG. 2, the CPU executes an IPL request in response to parity error detection and updates the contents of the memory 2. When this update is completed for all IPL data, these programs will be started.

In the above embodiment, a system example is shown in which there is one slave station B, but a network system in which a plurality of slave stations B exist may also be used. Furthermore, in the above embodiment, the damage to the memory contents of the main storage device 2 is detected by a parity error detection circuit using a integrity check circuit, but a watch dog timer error detection function is used to detect memory damage due to program runaway, etc. By having this, when a watch dog timer error occurs, the CPU
It is also possible to generate a forced interrupt for 1.

〔Effect of the invention〕

As described above, according to the present invention, the I/O from the master station to the slave station is
Since whether or not to perform PLt is decided based on the presence or absence of destruction of the contents of the main memory, it is possible to speed up the start-up time of normal system operation even when such destruction has not occurred. When the contents are destroyed, the program can be updated by the IPL, which has the effect of providing a system that has high operational reliability and can minimize system downtime.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram of a system that implements an initial program loading method according to an embodiment of the present invention, FIG. 2 is a flowchart showing the IPL operation of the present invention, and FIG. 3 is a block connection diagram of a conventional similar system. FIG. 4 is a procedure explanatory diagram showing the entire operation of conventional initial program loading. 1 is a CPU, 2 is a main storage device, 6 is a communication control device, 4 is an initial program loader, 5 is a data line, 6 is a main station device, 7 is an external storage device, 10 is a battery for memory backup, 12 is a parity check circuit, A is a master station, and B is a slave station. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Co., Ltd. agent Patent attorney 1) Hiroshi Sawa' 7 (2 others) -

Claims (2)

[Claims] (1) In an initial program load method in which a master station and a slave station are connected through a data line, and the master station loads a program into the main memory of the slave station in response to an initial program load request from the slave station, the slave station is provided with a memory backup battery that protects the main storage device, and when the voltage of the memory backup battery drops below a predetermined value, it enables the initial program load from the main station to the main storage device. An initial program loading method characterized in that when the voltage exceeds the predetermined value, a program already stored in the main memory is started immediately. (2) When a memory parity error is detected after the main memory is started, the contents of the main memory are loaded by the program from the master station in response to a request from the slave station to load the initial program to the master station. 2. The initial program loading method according to claim 1, wherein the initial program is updated.