JPS61292413A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit with logic circuit constitution having high speed operation, stable transmission characteristic, ease of manufacture process and high circuit integration by adopting an enhancement FET for both a load FET and a drive FET and inserting a Schottky barrier diode between the power supply and a gate of a load FET. CONSTITUTION:The enhancement FET is adopted for both the load FETQ1 and the drive FETQ2 and the Schottky barrier diode D is inserted between the power supply VDD and the gate of the load FETQ2. Thus, the inserted diode and a diode constituting a gate itself are connected in series, and two Schottky barrier diodes connected just in series are connected between the drain and source of the load FETQ1, then the gate-source voltage Vgs and the drain-source voltage Vds of the load FETQ1 are expressed in the relation of Vgs=(1/2).Vds and the FET operation is attained at the stable saturation region.

Description

[Detailed Description of the Invention] [Summary] In a logic circuit format using a semiconductor device, an enhancement type F in which the gate and drain are short-circuited with a diode is used.
By using an ET (field effect transistor) as a load and an enhancement type FET as a drive,
It has fast operating speed, a wide range of operating power supply voltages, sufficient margin for stable transfer characteristics, and can be configured with only FETs with one type of threshold voltage, simplifying the manufacturing process. Provided is a semiconductor integrated circuit that can improve yield.

C. Field of Industrial Application] The present invention relates to a semiconductor integrated circuit including a logic circuit configuration that is high-speed, has a large operating margin, and can improve manufacturing yield.

In recent years, gallium arsenide (GaAs) has begun to be put to practical use in high-speed logic circuits, but many of the current GaAs logic circuits use MESFETs (MESFETs) with different threshold voltages Vth.
DCFL (Direct Coupled FET L
gic), or normally-on (Normal) using depletion type PET with one type of threshold voltage Vth.
mally ON) type BFL (Buffered F
ETLogic) and 5DFL (Schottky D
It is a logic circuit such as iode PET Logic).

The former is difficult to control the manufacturing process, and the latter consumes a large amount of power and occupies a large area, making it unsuitable for integration, so improvements are desired.

[Conventional technology]

FIGS. 2(1) to 2(4) are circuit diagrams of conventional inverters, respectively.

Here, an inverter will be explained as a basic structural unit of a logic circuit.

Ql is the load Fil! T, Qt is the driving PET, V
an, vss are voltage at, ■, input terminal, V out
is the output voltage, IN is the input terminal, and OUT is the output terminal.

FIG. 2(1) is a circuit diagram of the DCFL.

In the figure, load F[! The transistor symbol using the double line T Ql indicates a normally-on depletion type FET, and the normal transistor symbol for the drive FHT Qz indicates an enhancement transistor that turns on when a voltage higher than the threshold voltage V is applied to the gate. Hail mold PET.

MESPET) Since the logic amplitude is small at 0.7 to 0.8V and the operating margin is small at 0.2 to 0.25V, it is necessary to control the threshold voltage Vth with high precision, and its variation must be kept small. No.

Its control accuracy is stricter than that of normally-on circuits.

FIG. 2 (2) is an example in which both the load FET and the drive FET Qt are configured only with enhancement type FETs.

In this case, the gate of the load PET Ql is pulled up to the power supply ■, so the gate-source voltage g,
and the drain-source voltage Vds is “ ”J, ,
-V,,.

Therefore, the FET operation is performed in an unstable region, and the current flowing during logic operation changes greatly, making the transfer characteristics unstable. Therefore, it is difficult to put this circuit into practical use.

FIG. 2(3) is a normally-on circuit, which is a BFL circuit diagram.

The left side of the figure is an inverter (switching) stage, and the right side is a level shift stage (buffer).

Q is the input FET of the level shift stage 1Q4 is the gate
The constant current FET and ots whose sources are short-circuited are Schottky barrier diodes for level shifting.

In this case, all FETs are formed into depletion type.

The power supply voltage is Voo=1.2~1.5V, Vss=-1,0~
1.5V.

shall be.

In the level shift stage, the level is shifted by the built-in voltage of the diode DLs and output.

FIG. 2 (4) is a normally-on circuit, which is a circuit diagram of 5DFL.

Also in this case, all FETs are formed into depletion type.

In the figure, the input signal is level-shifted by a diode OtS and then input to the next stage inverter.

In the normally-on circuits shown in Figure 2 (3) and (4), the FE
Since there is only one threshold voltage V of T, it is easier to control the characteristics than DCPL, but as mentioned above, it is unsuitable for integration.

[Problem that the invention seeks to solve]

The above conventional examples are (1) High-speed operation possible, (2) Stable transfer characteristics; (3) Easy to control manufacturing process; (4) High integration is possible by reducing power consumption and occupying area It was not possible to satisfy all of the above conditions.

[Means for solving problems]

The solution to the above problem is to use an enhancement type load FET (Q) with a diode (D) connected between the gate and drain.
1) A semiconductor integrated circuit according to the present invention including a logic circuit configuration having a drain connected to the source of the FET (Q1), and an enhancement type drive FET (Qz) that inputs a signal from the gate and outputs it to the drain. This is achieved by

[Effect]

In the logic circuit according to the present invention, the load FET is
Both T and QZ use enhancement type FETs,
A Schottky barrier diode D is inserted between the power supply Vfltl and the gate of the load FET Qt.

In this way, the inserted diode and the diode that constitutes the gate itself are connected in series, and the two Schottky barrier diodes connected in series are connected between the drain and source of the load PET Q. Therefore, the gate-source voltage v of the load FET Q,
,, and the drain-source voltage Vo is vs-=(1/2) Vas.

Therefore, the FET operation is performed in a stable saturation region.

In addition, manufacturing is easy because one type of FET is used,
And Schottky barrier diode D is load FET Q+
Even if it is made sufficiently small, it does not greatly affect the logic operation, so the occupied area has little effect, so it does not impede high integration.

Furthermore, the voltage applied to the gate of the load FET Q changes depending on the logic operation, and the logic threshold also changes with changes in the power supply voltage VDD, so the stability of the transfer characteristics is lower than that of a DCFL. Not much different.

For this, the supply voltage ■. , it is also possible to control the operating speed of the circuit.

Also, compared to DCFL, the output voltage V out is
Since it is not connected to the gate of Tg, the load capacity is small, which is advantageous for high-speed operation, and the signal path can be simplified.

〔Example〕

FIG. 1 is a circuit diagram of an inverter according to the present invention.

In the figure, Q+ is the load FET, Qz is the drive PET
, D is a Schottky barrier diode, MDIll is a power supply voltage, Vi is an input voltage, V oulL is an output voltage,
IN is an input terminal, and OUT is an output terminal.

Load FET Q and drive FET (h are both enhancement type FETs, and a Schottky barrier diode D is inserted between the power supply (2) and the gate of the load FET Q2.

A gate circuit using an inverter using the above circuit configuration will be shown below.

FIGS. 3(11 and 2) are circuit diagrams of logic circuits according to the present invention, respectively.

Figure 3 (1) is a 3-person NOR circuit, Figure 3 (2) is a 2-person NOR circuit.
It is a human-powered NAND circuit.

A semiconductor integrated circuit having a logic circuit configuration that is operable, has stable transfer characteristics, is easy to manufacture, and can be highly integrated can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an inverter according to the present invention, and FIG.
1 to (4) are circuit diagrams of inverters according to conventional examples, and FIGS. 3 (1) and (2) are circuit diagrams of logic circuits according to the present invention, respectively. In the figure, ``gate'' is the inverter's load FET, D is the Schottky barrier diode, and Q2 is the inverter's drive FET. Q3 is the manual FET of the level shift circuit, Q4 is the constant current FET of the level shift circuit, OLS is the level shift diode, IN is the input terminal, OUT is the output terminal, ■0, ■5. is the power supply voltage, V in is the input voltage, ■. □ is the output voltage for each tree; EhglJ early 3rd mouth

Claims (1)

[Claims] An enhancement type load transistor (Q_1) with a diode (D) connected between the gate and drain, the drain connected to the source of the load transistor (Q_1), a signal inputted from the gate, and the drain connected to the source of the load transistor (Q_1). 1. A semiconductor integrated circuit comprising a logic circuit configuration having an enhancement type drive transistor (Q_2) that outputs an output signal.