JPS60160217A - Fet source coupling logic circuit - Google Patents

Abstract

PURPOSE:To realize an FET source coupling logic circuit with less DC level fluctuation attended with changes in mark rate in an output signal by attaining the reduction of voltage to a drain supply voltage to a differential switch part by means of a Schottky barrier diode or a junction diode and setting the FET of a source follower to a degree where its gm is not decreased extremely. CONSTITUTION:Since any of FETQ1 or Q2 is turned on, a current flowing to the differential switch part is a constant current VD at steady-state because of the function of an FETQ5 and a foward voltage drop of diodes Di1-im constituted by Schottky diodes is constant. A voltage drop of ID.RS is produced by a Q3 or Q4 with a forward resistances RD of the Q3 and Q4, and its output voltage value V is VDD-(mVbi+IDRS) when the Q1 or Q2 is turned off. Thus, the current flowing to the Q6/Q7 is constant and a defect that the pulse width is changed because of the fluctuation of the DC level having been generated in a conventional system attended with the mark rate of the output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a logic circuit configured in addition to a metal semiconductor FET, and in particular to a source-coupled PET logic (SCF).
Regarding improvement of L).

(b) Background of the Technology Figure 1 shows a side view of the configuration of a conventional 5CFL. The configuration shown in the figure is an OR/NOR circuit. In the diagram, Q1-9 are F
The ET elements D1-n are diodes. Q 1+ Q
2 is for differential switch, Q31Q4 are Ql and Q respectively
2 for active load resistance, Q5 for constant current active resistance for Ql and Qz, Q61Q7 for source follower,
Q8. Q9 is Q6. Q7 is for constant current active resistance and Dl-0 is for level shift. 5CFL as well, as shown in FIG. 1, a pair of FET elements Q1. The sources of Q2 are connected to operate, and the signal input (IN) side, for example, when the gate voltage Vcs1 of Ql is higher than the reference voltage (Vref) side V (Na 2), V
Ql given 6s l becomes conductive (turned on) and Ql on the reference side becomes non-conductive (off), conversely VGBI (
When VGB2 = Vref, Qi is off and Ql is on, and in a steady state, current flows through either F'ET of the pair Ql or Ql.

If the reference voltage Vref for the comparison operation is set to positive logic, for example, it is set to an intermediate value between the high logic level threshold Vshh and the low logic level V+hl. Also, usually Ql, Ql
Q6. to increase the load capacity of the switching output by the input signal and to return the input signal to a high or low logic level for matching with subsequent circuit units. A source follower section including Q7 and DI-n for level shifting is added.

However, unlike the ECL in which all the constituent elements are operated in a non-saturation region of off or active regions, the 5CFL is different in that switching operations are performed in an off or saturated region.

(e) Prior art and problems In the 5CFL with the configuration shown in Figure 1, the output of the differential switch section due to Q 1 + Q 2, for example, Ql is turned off and Q
When the input to Q6 is at a high level, Q6 is of course turned on, but the output voltage of Ql, that is, the input voltage VGS6 to Q6 is close to the drain supply voltage Vnn, and Q6 is in an unsaturated state. Since the conductance 8m6 decreases and the input capacitance 1ctn6 of Q6 increases to, for example, four times the input capacitance when there is no signal, there is a drawback that the rise time of the output signal in response to the input signal pulse increases.

Ci n= Ccso4m+Cao (Vns) ・
・・・・・・・・・ Equation (1) and Q8. If the constant current function by Q9 is perfect, the current flowing to Q6 will be constant and OUT
The signal obtained at 1 has ideal operation with only a voltage change, but in an overdriven state, it increases/decreases in response to the on/off of Q6, so the output signal changes to DC depending on the high/low level of the input signal. 75fc has the disadvantage that level fluctuations occur and the pulse width changes with the mark rate.

The above drawback is the differential switch section (h
+Q2 voltage to source follower s Qe + Q7
This can be solved by lowering the supply voltage to Q3. A method of inserting a constant resistance between Q4 and Vpp has been proposed, but in the case of integrated circuits using gallium arsenide (GaA8) semiconductor substrates, it has not been possible to realize a constant resistance with high precision due to the substrate and processing process, so the resistance value It had the disadvantage of large variations and poor stability.

(d) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks by reducing the drain supply voltage to the differential switch section to a voltage lower than that of the source follower section, instead of reducing the voltage by using a constant resistor with large resistance value variations in the conventional method. Achieve voltage reduction using a shut-key barrier diode or junction diode with a stable drop value, suppress overdrive to the source follower section, and keep the source follower FET as close to the unsaturated region as possible. Set the input capacitance Ci to such an extent that gm does not drop excessively.
This is intended to prevent the rise delay of the output signal due to an increase in n, and to provide a direct response to the change in mark rate in the output signal while minimizing the current fluctuation of the follower FET.

(e) Structure of the Invention The above object is to provide a logic circuit composed of metal semiconductor FETs and consisting of a differential switch section and its source follower section, which compares an input signal level with a reference voltage or voltage to form a differential switch. a first and a second FET element; The third element serves as the active load resistance of the second FET element.
The fourth F'ET element and the first. A constant current active load resistor connects both source terminals of the second FET element to the source supply power supply, and a drain supply power supply to the differential switch section consisting of the fifth FET element is connected via a diode in which one or more of them are connected in series. 1. ．． The output voltage of the first or second FETT element is lowered by the forward voltage drop caused by the diode toward the source supply power source, and 6. This can be achieved by providing a PET connection logic circuit characterized in that it is configured to be the driving voltage of the seventh FET element.

(f) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a side view of the configuration of a FET source coupled logic circuit (SCEL) in one embodiment of the present invention.

In the figure, Ql~9 are F''ET elements, D1~n and D
i+ to im are diodes. Components showing the configuration in the figures having the same reference numerals as those of the conventional components have functions and characteristics common to those of the conventional components. Therefore, the configuration of this embodiment shown in FIG. 2 is the same as the conventional configuration shown in FIG. 1 except for Di+ to im. In the steady state, the current flowing through the differential switch section is such that Ql or the tip of Ql is on, and a constant current I5+ flows due to the function of Q5, and Dit~1 composed of, for example, a Shosotky dynard.
The forward voltage drop value of m is constant. Therefore vI′1+
If '1 is constant, mIIvbi by Dil-im
, in the case of GaAS, for example, the built-in voltage Vb i ~
A voltage drop of 0.76V is generated. If the forward resistance of Q3 and Q4 is RD, then Ib1 is increased by Q3 or Q4.
- A voltage drop of R, 4 occurs, and when Q+t or Ql is off-, the output voltage value V = VDD - (mVbi +I
a+Rs )(!: fishi) Compared to the conventional case without Di1~im, it is reduced by mVb i, so m is set appropriately and VllS6 >Vp≧VDD-(mVb i+
If IDR8), the Vo3'i of Q6 can be reduced and it can be operated in the saturation region without over-driving, so VDS6 ==mVbi+IoRs can be reduced without reducing the transconductance of Q6 (9m). According to the above-mentioned equation (1), the input zero 1 cin does not increase, and therefore the output signal can have a high-speed rise.

Here, Vp is the pinch-off voltage, and V+h is the high-level logic threshold.

Therefore, the current flowing through Q6/Qr is constant, and stable and high-speed operation can be achieved, which eliminates the drawback that the pulse width changes due to fluctuations in the DC level that conventionally occur due to changes in the mark height in the output signal. 5 CFL can be obtained.

Although the above example uses Di1 to im and m Schottky diodes, the selection of vBi in GaAs and '
Depending on the settings of VDD and Vss, there are cases where the number m can be realized with a minimum of one.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a metal semiconductor FET is manufactured using materials such as Ga AB and Q, ~9°D.
Since it is not possible to obtain a 5CFL that achieves stable and high-speed operation using a constant Vbi obtained by the bonding process common to In and Di1 to im, it is extremely useful in the configuration of logic circuit elements obtained by integrating these. It is.

[Brief explanation of the drawing]

FIG. 1 is a side view of the configuration of a Worth coupled FET logic circuit (5CFL) using a conventional metal semiconductor FET, and FIG. 2 is a side view of the configuration of a 5CFL using a metal fist semiconductor F''ET according to an embodiment of the present invention. In the figure, Q1 to Q9 are FET elements, Dl-1 and Di
r-im is a diode. ” ss Vss 0σγI θllrz

Claims (1)

[Claims] In a logic circuit composed of metal semiconductor FETs and consisting of a differential switch section and its source follower section, the first section compares the input signal level with a reference voltage to form a differential switch. a second FET element, the first. 2nd FE
The third element is the active load resistance of the T element. The fourth FET cue and the first FET. The drain supply tube to the differential switch section consisting of the fifth FET element, which serves as a constant current active load resistance that connects both source terminals of the second FET element to the source supply power source, is connected to a diode in which one or more sources are connected in series. the first or second FE.
The output voltage at the T element is lowered by the forward voltage drop caused by the diode toward the source power supply side, and the sixth. 7th
A FET source coupling logic circuit characterized in that it is configured to use a driving voltage of an FET element.