JP2800562B2 - Compound semiconductor logic circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit comprising compound transistors, and more particularly to a logic circuit constituting a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, this kind of compound semiconductor logic circuit has been known as a BFL circuit (Buffered FET Logi).
c). Hereinafter, a conventional BFL circuit will be described with reference to the drawings.

FIG. 5 is a circuit diagram of a conventional inverter, and FIG. 6 is an operation explanatory diagram of FIG. The conventional inverter has a depletion type transistor Q10 to Q13 and a diode D
1, D2. This inverter has VSS1 (-2.0V) and VSS2 (-5.2) in addition to the ground voltage.
Are required to drive the additional capacitance C1. Hereinafter, the circuit operation of FIG. 5 will be described with reference to FIG.

First, at time t1, when the input signal φIN3 starts transitioning from “high” (H) level to “low” (L) level, at time t2, the node N5 and the output signal φOUT3 transition from L level to H level. Is started, and becomes H level at time t5. Then, at time t6, the input signal φIN3 becomes L
When the transition from the level to the H level starts, the node N5 and the output signal φOUT3 start to transition from the H level to the L level at the time t7, and go to the L level at the time t10.

FIG. 7 shows the operating currents I4 and I5 of FIG.
As shown in the figure, when the input signal φIN3 is at the L level and the H level, the operating current I5 flowing through the transistor Q13 hardly changes and is substantially constant.

[0006]

The conventional inverter circuit composed of a compound semiconductor BFL circuit is a depletion type transistor (hereinafter referred to as a D-FET).
A steady current flows by the low current source of Q13. here,
0.5 PF additional capacitance C1 and D-FETs Q12 and Q13
And the gate width of the diodes D1 and D2 is 30 μm,
The gate widths of ETQ10 and Q11 are 5 μm and 7, respectively.
If it is 5 μm, the response time from time t2 (or t7), which is the intermediate potential of the input signal φIN3, to time t4 (or t9), which is the intermediate potential of the output signal φOUT3, is about 2
Although the high-speed operation is performed at 00PS, the operation current I5 is
The current is almost the same whether IN3 is at H level or low level, and the power consumption is 2.8 mA × 5.2 V = 14.6 m.
W, resulting in a problem of high power consumption.

An object of the present invention is to provide a compound semiconductor logic circuit capable of reducing power consumption.

[0008]

According to the present invention, there is provided a logic circuit comprising:
Depletion type transistor (hereinafter D-FET)
) Is connected to a first power supply, a gate and a source are respectively connected to a first node, and a gate and a drain of a first enhancement transistor (hereinafter, referred to as an E-FET) are connected to a second node. A source connected to the second power supply, a drain of the second E-FET connected to the first power supply, a gate connected to the first node, and a source connected to the third node, respectively; The drain of the FET is connected to the third node, the gate is connected to the second node, and the source is connected to the second node.
And the drain of the second D-FET is connected to the first power supply, the gate is connected to the third node, and the source is connected to the output signal. The drain of the third D-FET is connected to the output signal. A gate and a source are respectively connected to the second power source, a gate and a source are commonly connected, and a source of a D-FET whose drain is connected to an input signal is connected to the gate of the input E-FET. Node and the second
N (n: positive integer) in series or m (m: positive integer) in parallel between the nodes.

[0009]

The logic circuit of the compound semiconductor according to the above-described structure functions with only a single second power supply in addition to the first power supply.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is an inverter circuit diagram of a first embodiment of the present invention. Q1, Q2, Q7, and Q8 are depletion type transistors (hereinafter, referred to as D-FETs), and N1 to N4 are nodes. QIN0 is an input signal, and QOUT1 is an output signal. As compared with the conventional example of FIG.
2 (-5.2V) power supply, VSS1 (-2.0V)
V) only. The D-FET Q1 is E-
This is for reducing the forward current of the gate Schottky of the FET Q3.

Hereinafter, referring to the operation explanatory diagram of FIG.
The operation of the embodiment will be described. First, at time t1, input signal φI
When N0 starts transitioning from the H level to the L level, the nodes N2 and N4 and the output signal φOUT1 start transitioning from the L level to the H level at time t2, and go to the H level at time t5.

At time t6, input signal φIN0 goes low.
When the transition from the level starts to the H level, the nodes N2 and N4 and the output signal φOUT1 start transitioning from the H level to the L level at time t7, and go to the L level at time t10.

The gate width (Wg) of the D-FETs Q1 and Q2 in FIG. 1 is 3 μm, and the Wg of the E-FETs Q3 and Q4 is 6 μm.
m, Wg of E-FET Q5, Q6 is 10 μm, D-FE
Wg of TQ7 and Q8 is 30 μm, and additional capacitance C1 is 0.5
Assuming PF, the response time from time t2 (or t7), which is the intermediate potential of input signal φIN0, to time t4 (or t9), which is the intermediate potential of output signal φOUT1, is about 20.
At 0PS, the same high-speed operation as the conventional example is performed.

FIG. 3 shows operating currents I1 to I3 of the logic circuit. This logic circuit is a switching circuit unit 100
And the buffer circuit unit 200.

The operating current I of the switching circuit section 100
1 and I2 hardly flow, and the average power consumption is 1 mW or less. On the other hand, the buffer circuit unit 200 includes a D-FET Q8
Current always flows through the constant current source, but the power supply voltage is changed to VSS1 (−
2.0 V), so that the average power consumption is about 4 mW.

Therefore, the power consumption of the logic circuit can be reduced to 1/3 or less as compared with the conventional example.

In order to reduce the gate Schottky forward current of the input E-FET Q3, the D-FET Q1
Is added, and a logic operation can be stably realized even at an excessive input signal level.

FIG. 4 shows a two-input NOR according to a second embodiment of the present invention.
It is a circuit diagram of a circuit. FIG. 4 differs from FIG. 1 only in that the logic operation of the entire circuit is changed by increasing the number of input circuit FETs Q1 and Q9 in parallel, and the basic operation is the same. Detailed description is omitted.

[0019]

As described above, the present invention provides an E-FE
By using a basic circuit using T and D-FET,
Since the -5.2V power supply can be omitted and a -2V single power supply can be used, the same high-speed operation as the conventional example can be ensured, and the power consumption can be reduced to about 1/3 of the conventional example. Have.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an inverter circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a graph showing an operation current of the first embodiment.

FIG. 4 is a circuit diagram showing a two-input NOR circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional inverter circuit.

FIG. 6 is a timing chart for explaining the operation of the conventional example.

FIG. 7 is a graph showing an operating current of a conventional example.

[Explanation of symbols]

 Q1, Q2, Q7 to Q13 D-FET Q0, Q3 to Q6 E-FET φIN0 to φIN3 Input signal φOUT1 to φOUT3 Output signal N0 to N5 Node name C1 Additional capacitance VSS1 -2V power supply VSS2 -5.2V power supply I1 to I5 Current 100 switching circuit section 200 buffer section

Claims (3)

(57) [Claims] 1. A drain of a first depletion type transistor is connected to a first power supply, and a gate and a source are respectively connected to a first node. A source and a gate of the first enhancement type transistor are connected to a second node. A second power supply, a drain of the second enhancement transistor connected to the first power supply, a gate connected to the first node, and a source connected to the third node;
The drain of the enhancement type transistor of the first embodiment is connected to the third node, the gate is connected to the second node, and the source is connected to the second node.
And the drain of the second depletion type transistor is connected to the first power supply, the gate is connected to the third node, and the source is connected to the output signal.
An input in which the drain of the depletion type transistor is connected to the output signal, the gate and the source are connected to the second power source, the gate and the source are connected in common, and the source of the depletion type transistor which supplies the input signal to the drain is connected to the gate. A compound semiconductor logic circuit comprising a plurality of enhancement type transistors connected between the first node and the second node. 2. The device according to claim 1, wherein said plurality of input enhancement transistors are connected in series.
The logic circuit of the compound semiconductor according to the above. 3. The device according to claim 1, wherein said plurality of input enhancement transistors are connected in parallel.
The logic circuit of the compound semiconductor according to the above.