JPS61290560A - Input signal sensing system - Google Patents

Abstract

PURPOSE:To select only an effective signal, to reduce a program quantity, to reduce a burden applied to a CPU, and to execute an operation with a high efficiency by providing a chatter eliminating circuit and an effective level detecting circuit on all of plural input ports. CONSTITUTION:When a level variation from the outside appears in an input terminal P1 of an input port L1, F1 and F2 of an FF are operated by the first and the second clocks PHI1, PHI2 in four pieces of scan clocks, in order to discriminate whether its level variation is an effective variation or a chatter which becomes a fault. In case of a different state of the input terminal P1 has been sampled at two points of the fall of the clocks PHI1, PHI2, the output of an exclusive NOR gate E1 becomes '0', it is regarded as a chatter signal, and it is not executed to set the input port L1 to a register F3. Also, in case of P1 potential has sampled the same state at two points of a fall of the clocks PHI1, PHI2, the output of the NOR gate E1 becomes '1', its value is regarded as an effective level, and its state value is set to the register F3 at a rise of a scan clock PHI3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an input signal sensing method, and more particularly to an input signal sensing method in a system that uses a CPU to monitor signals at a plurality of input ports.

(Prior Art) A typical example of the configuration of this type of input signal sensing system is shown in the block diagram of FIG. 4. Among these, first of all, in FIG. 4 (I), the crty (central processing unit) has an input signal sense program in its main program, and this program autonomously controls the input signal of the input port. The changing state was detected (sense).

Also, in Figure 4 ω), the CPU has a program in its main program that sets a timer, and this timer generates an interrupt to sense the state of the input signal at the input port.

As described above, in the conventional input signal sensing method, the input port is sensed only at a fixed period, and it is largely dependent on the program.

(Problems to be Solved by the Invention) However, in the input signal sensing method with the above configuration, the amount of programs that must be set for the operation for sensing the input port is large.
In addition, due to program processing, it is not possible to respond quickly to changes in input signals, and furthermore, when the CPU senses an input date, a chatter signal appears at the input port. However, there was a problem in that the CPU was unable to determine the presence of chatter signals and detected incorrect data.

This invention eliminates all the problems that the prior art had, reduces the amount of programs and reduces the load on the CPU, and eliminates unnecessary signals such as chatter at the input port so that only valid signals are used. It is an object of the present invention to provide an excellent input signal sensing method that allows a CPU to quickly respond to changes in the state of an input signal.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a system in which signals of a plurality of input ports are monitored by a CPU using an interrupt controller.
The first . of scan clocks connected in parallel to the input terminals and having the same period but different phases. The exclusive furgate E□ operates only when the outputs of the flip-lag frogs F□, F, which are operated by the second clock, and the output of this flip-flora 7'F1pF* are at the same level.
a chatter signal removal circuit comprising a chatter signal removal circuit, and an effective level signal output from the chatter signal removal circuit and the scan signal.
3rd clock. And dirt A1 with the 4th clock
Registers I's and F operated by each output of mAm
n and the output signal of the flip-flop F are input to register F3, and the output of register F3 is input to register F4, and register F3 and register F are input.
an effective level detection circuit consisting of an exclusive or f-to E that operates only when the respective output levels of four do not match, and a flag register F that operates based on the output from this or 11-dart E2. By repeating the scan cycle of the scan clock, the valid level signals selected at the plurality of input ports are OR-r-to-o1.
The signals of a plurality of input ports are monitored by transmitting the signal to the interrupt controller via the interrupt controller and notifying the CPU by the interrupt controller.

(Function) According to the present invention, since the input signal sensing circuit is configured as described above, even if an irregular signal such as chatter is input to the input terminal, the chatter signal removal circuit in the input port detects the chatter signal. The effective level detection circuits subsequent to this chatter signal removing circuit operate to select and detect only effective level signals. Then, this valid level signal notifies the CPU via the interrupt controller IRC that there has been a valid level change at the input port, so the CPU detects the output of register F3 only at this time and clears the flag register Fse. Prepare for the state change of the input terminal P□ of the next input port. Therefore, the above problem can be eliminated.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention. In the figure, 1 is an input port, one of which is drawn as a representative, 2 is an interrupt controller, and 4 is an input port.
3 is a CPU which has a main program 4 inside.

FIG. 2 is a circuit diagram showing an embodiment of the present invention, and in the figure,
L1 to Ln are input dates, P1 to Pn are input ports L1
~Ln input terminals, input ports L2~Ln are input/-
) The circuit configuration is shown as a representative example of the input port.

First, in the input port L0, F□ and F2 are each flip-frog, and both D terminals are connected to the input port terminal P, so a change in the state of the input appears as it is at the D terminal, and the scan clock φ , and φ2 are connected to the G terminal, and when φ□ and φ are @1'', D
Set the terminal status value to the Q terminal. E□ is Exclusive Noah Dart Ash, Flip Frog F1
The output is '1' only when the outputs of F2 and F2 are the same,
Its output is connected to A2. AND gate A, A2 outputs the output 11'' of exclusive NOR gate E8 only when scan clocks φ3 and φ4 are ``1''. F3,
F4 are flip-flops, and r −
) A□ gA2 outputs are connected to the G terminal, respectively,
When the output of AND dirt A□ tA2 is @1', the output of flip-flop F□ IF is output to the Q terminal.

F2 is exclusive-or-dirt, and outputs "1" only when the outputs of flip-flop F3 and flip-flop F4 are different.

F is the flip-flop to D in the crystal flag register.
The output of exclusive OR gate E2 is connected to its G terminal, and the F terminal is always kept at high level.
When the output of 2 becomes "1", @1" is set to the output terminal Q.

Note that, as described above, the other input ports L, -Ln are also configured in the same manner as the input port L1.

Then, the output from each input port L1 to L is input to the OR gate O, and this OR dirt 0! The output of is connected to the interrupt controller IRC, and this output is connected to the CPU.

Next, the operation of this system configured as above will be explained.

Now, when a level change from the outside appears at the input terminal P□ of the input port L□, it is necessary to identify whether the level change is a valid change or a chatter that is an obstacle. The first scan clock among four scan clocks with the same period and different phases. The second clock i.e. φ
1 and φ2 operate the flip 70TZO F□ IF2.

It is assumed that this scan clock and the potential of the input terminal P1 have a relationship as shown in the waveform diagram of FIG.

If we sample different states of the input terminal P1 at two points: the falling edge of φ□ and the falling edge of φ2, that is, t□
Sometimes the output of exclusive Noah gate E□ is @
0 #, this is regarded as a chatter signal and is not set in register F3 of input port L1.

However, flip flora 7°F1, F27jEφ□
If the same state of P□ potential is sampled at two points, the falling edge of The state value is set in the register F1 at the rising edge of the scan O clock φ3.

And with Exclusive or Dirt E2,
The contents of input port register F, are compared with the previous sampled state value of input port register F4, and if they are the same, the output of exclusive-or gate E is “O”.
# and flag register F are not set, and only when the two do not match, the output of F2 becomes "1#", and at that timing, flag register vsK "1" is set.

Furthermore, at the rising edge of φ4, the state value of the input port register F, which has just been sampled, is transferred to the register F for the next comparison.
Set it to 4.

In addition, to indicate that there has been a valid level change at the input terminal P□, a signal Mlml is output from the Q terminal of the flag register F6, and is sent to the interrupt controller I through OR/f-)01.
Inform CPH using RC.

Only at this time, the CPU detects register F3, clears flag register F, and prepares for the next state change at input terminal P.

The above is the operation of the input port during one scan cycle in the input signal sensing method according to the present invention, and this operation is repeated every scan cycle.

(Effects of the Invention) As explained above, according to the present invention, by providing a chatter removal circuit and a valid level detection circuit for all of the plurality of input ports, only valid signals are selected and this signal is used as an interrupt signal. By using a circuit system that operates the CPU by notifying the CPU by the controller, it is possible to reduce the amount of programs, reduce the burden on the CPU, and operate the CPU with high efficiency. In addition, it is possible to expect effects such as speeding up the CPU's response to changes in the input level at the input port.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a specific configuration of the main part of the present invention, Fig. 3 is a waveform diagram of the main part of the present invention, and Fig. 4 is a conventional It is a block diagram showing a method. F□～F,...Flip frog, E-engine...exclusive noah gate, E2...exclusive or dirt, A□ gA2...and goo), O□ ...or goo)% p, ~Pn...input terminal, L1~Ln...input port.

Claims (1)

[Claims] In a system in which signals of multiple input ports are monitored by a CPU, all input ports are connected to input terminals in parallel and are respectively operated by the first and second clocks of scan clocks having the same period and different phases. A chatter signal removal circuit consisting of flip-flops F_1 and F_2 and an exclusive NOR gate E_1 that operates only when the outputs of the flip-flops F_1 and F_2 are at the same level; AND gates A_1, A of the valid level signal and the third and fourth clocks of the scan clocks;
The output signals of registers F_3 and F_4 operated by the respective outputs of register F_2 and the flip-flop F_1 are inputted to register F_3, and the output of register F_3 is inputted to register F_4, so that each output level of register F_3 and register F_4 is Exclusive or gate E_2, which operates only in case of mismatch, and this or gate
and a flag register F_5 operated by the output from the gate E_2, and by repeating the scan cycle of the scan clock, the valid level signals selected at the plurality of input ports are detected by the OR gate O_1. An input signal sensing method characterized in that signals of a plurality of input ports are monitored by transmitting signals to an interrupt controller IRC via an interrupt controller and notifying a CPU by the interrupt controller.