JPS61290553A - チヤネル装置 - Google Patents
チヤネル装置Info
- Publication number
- JPS61290553A JPS61290553A JP60133402A JP13340285A JPS61290553A JP S61290553 A JPS61290553 A JP S61290553A JP 60133402 A JP60133402 A JP 60133402A JP 13340285 A JP13340285 A JP 13340285A JP S61290553 A JPS61290553 A JP S61290553A
- Authority
- JP
- Japan
- Prior art keywords
- address
- ram
- data
- dat
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60133402A JPS61290553A (ja) | 1985-06-19 | 1985-06-19 | チヤネル装置 |
| US06/874,995 US4797812A (en) | 1985-06-19 | 1986-06-16 | System for continuous DMA transfer of virtually addressed data blocks |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60133402A JPS61290553A (ja) | 1985-06-19 | 1985-06-19 | チヤネル装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61290553A true JPS61290553A (ja) | 1986-12-20 |
| JPH0370257B2 JPH0370257B2 (enrdf_load_stackoverflow) | 1991-11-07 |
Family
ID=15103907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60133402A Granted JPS61290553A (ja) | 1985-06-19 | 1985-06-19 | チヤネル装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61290553A (enrdf_load_stackoverflow) |
-
1985
- 1985-06-19 JP JP60133402A patent/JPS61290553A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0370257B2 (enrdf_load_stackoverflow) | 1991-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4797812A (en) | System for continuous DMA transfer of virtually addressed data blocks | |
| US4163280A (en) | Address management system | |
| US4896262A (en) | Emulation device for converting magnetic disc memory mode signal from computer into semiconductor memory access mode signal for semiconductor memory | |
| US4682305A (en) | Storage system | |
| EP0076629A2 (en) | Reconfigureable memory system | |
| US4495564A (en) | Multi sub-channel adapter with single status/address register | |
| EP0260433B1 (en) | Multi-address space control method | |
| US4513369A (en) | Information processing system | |
| EP0032136B1 (en) | Memory system | |
| JPS61290553A (ja) | チヤネル装置 | |
| JPS6011950A (ja) | 二重化メモリシステム | |
| US4882672A (en) | System for initialization of channel controllers utilizing address pointers calculated from multiplying sizes of data fields with device numbers | |
| JPS61290552A (ja) | チヤネル装置 | |
| CN1004945B (zh) | 地址控制装置 | |
| JPS5845116B2 (ja) | 二重化記憶装置 | |
| JP2600376B2 (ja) | メモリ制御装置 | |
| JPS61290554A (ja) | チヤネル装置 | |
| KR900009212Y1 (ko) | 어드레스 제어장치 | |
| EP0358224A2 (en) | Semiconductor disk device useful in transaction processing system | |
| JPS6126700B2 (enrdf_load_stackoverflow) | ||
| JPS62187956A (ja) | Dma制御方式 | |
| JPS6218074B2 (enrdf_load_stackoverflow) | ||
| KR20010028615A (ko) | 교환기의 이중화 장치 | |
| JPS58169398A (ja) | メモリ・システム | |
| JPS6013497B2 (ja) | キャッシュメモリの診断方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |