JPS61289599A - Program memory circuit - Google Patents

Abstract

PURPOSE:To obtain a program memory which can recover to the previous condition instantaneously by providing a logic circuit to indicate the reading from the second ROM when the output signal of the block selection from a block selecting circuit exists and indicate the reading from the first ROM when the output signal does not exist. CONSTITUTION:When a memory reading indicating signal 8 and an address signal are sent from a CPU 1 and the correcting program to the selected block is not written in the second ROM 4, a reading indicating signal 10 is generated by logical gates 17-20, and when the signal 10 is effective, the program is read from the first ROM 3. When the correcting program is written in the second ROM 4, a reading indicating signal 11 is generated by logical gates 17-20. On the other hand, the address signal of the address belonging to the block of the second ROM 4 shown by the signal which comes to be H of the signal lines of Q1-Q32 by an encoder 14 is generated, and when the signal 11 is effective, the correcting program is read from the second ROM 4. Thus, the previous condition is recovered easily and the program can be efficiently corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program memory in which a program for a microcomputer system is written.

[Conventional technology]

Central processing unit for general microcomputer systems! 1 (hereinafter referred to as CPU), the start address after startup is determined to be the maximum or minimum address of the CPU's memory space. For example, in a CPU that starts from address θ after startup, a program for creating the system km is stored in the memory space starting from address 0. Furthermore, this program is written in a memory (hereinafter referred to as ROM) dedicated for continuous output so that it will not be erased even if the power is turned off.

In program maintenance, there is a method called patch modification to modify a program using depacking. This is a method of modifying only the instructions in the modified portion of the program memory.

Since it is not possible to directly patch the corresponding part of a program written in a ROM, conventionally the patch is modified to the same program as the contents of the ROM at another location, and the modified program is then patched separately. The program was modified by writing it into the ROM and replacing it with this title.

[Problem that the invention seeks to solve]

In the conventional method as described above, as the number of corrections increases, the number of problems used also increases, and when you make an incorrect correction, when you want to restore the previous state, the content of the ROM that was incorrectly corrected increases. Since it was difficult to determine the previous state, there was a problem in that the previous ROM had to be preserved.

This invention was made to solve the above-mentioned problems, and even if the number of modifications increases, there is no need to increase the number of ROMs used, and it is possible to immediately restore the state to the previous state. The purpose is to provide program memory that can be used.

[Ninth way to solve the problem]

The program memory according to the present invention is divided into a plurality of blocks including a first ROM in which a program is written and a predetermined number of bytes in this ROM, and correction is made for each block in which a block in which an error exists in the program is provided. A second ROM in which a program is written, a decoder that decodes the address signal from the CPU and selects a block to which the address indicated by the address signal in the first ROM belongs, and a modification program for the selected block. Second R
A block selection circuit that selects the written block when it is written in the OM, an encoder that creates an address signal of an address belonging to the selected second block, and a continuation instruction from the CPU. a logic circuit which instructs to read from the second ROM when a block selection output signal from the block selection circuit exists, and instructs to read from the first ROM when the output signal does not exist; It is prepared.

[Effect]

When the CPU instructs to read a program and sends an address signal, the decoder selects the block to which the address of the first pigeon indicated by the address signal belongs, and the block selection circuit transfers the modified program for that block to the second block. A search is made to see if the ROM K-it is written in. If it is not written, the logic circuit is instructed to read from the first R (M), and if it is written, it is read from the second R (M). Reading from the ROM is instructed, and an address signal of the address belonging to the next selected block of the second title is created in the encoder.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, (1) is the CPU, +21 is the program memory of this invention, and (3) is the program 't-8g.
1 ROM, +41 is wJ with correction program written.
2 ROM, 15) a control circuit that controls tit reading, (6) an address bus, +71t:t data bus, (8) a memory read instruction signal from the CPU [11], (9) a control circuit ( 5) Second RQM created in
+41 address signal address bus, (10) is a read instruction signal from the first ROMf31 created by the control circuit (5), (11) is the second ROM created by the control circuit 15) This is a read instruction signal from +41.

FIG. 2 is a block diagram showing the control circuit (5) part of FIG. 1, and in the figure, +61, +81, +91
, (10) and (11) indicate the same bus or No. 16 as the same reference numerals in FIG. The decoder (13) selects the block to which the address indicated by the block belongs, and the modification program for the block selected by the decoder (12) is the second RO.
A block selection circuit selects the written block when data is written to M +41, and (14) is an address signal of an address belonging to the block of ROM 2 +41 as soon as it is selected by the block selection circuit (13). (15) is a signal generation circuit that generates a program read instruction signal (16) using an address signal from the CPU fil and a memory read instruction signal (8); (17)
, (18), (19), and (20) are logic gates.

FIG. 3 is an explanatory diagram showing a signal line connection method in the block selection circuit (13).

In this embodiment, the first ROM 131 and the second ROM
+41 with a capacity of 4 bytes each, divided into 32 blocks of 128 bytes t-1 block, and a correction program for each block for the block where an error exists in the first RQM +31 program is executed. It is assumed that the data is written in the second ROM 141.

The block selection circuit (13) selects a signal line (address signal is O) for a signal indicating the block of the first ROM (+3) selected by the decoder (12). 32 signal lines up to P for the fifth block from 80H to FFFH) and a signal line for the signal indicating the block of second ROM +41 (Q
32 from l to Q3□), the first double shoulder (
The signal line for the block in which there is an error in the program in step 3) and the signal line for the second ROM +41 block in which the correction program and Durham are written are connected by a jumper wire (21). 2 doves (4
) is configured so that the block in which the modification program is written is selected. Figure 3 (al is R of 8g1
The relationship between the memory addresses of both blocks and the connection state in the block selection circuit (13) when the modification program for @4 block of OM 131 is written in the first block of the second ROM +4) Figure 3 tbl
This figure shows the case where the number of blocks of t-j program modification increases.

Address selection in the first ROM +3) is performed by the CPU
The second ROM
Address selection at +41 is done by encoder (14)
This is done using the address signal created in .

When a memory read instruction signal (8) and an address signal are sent from the CPU fil, a program read instruction signal (16) is generated in a signal generation circuit (15) and output. On the other hand, the decoder (12) decodes the address signal, selects the block to which the address indicated by the first ROM +31 address signal belongs, and selects the block from Po to P3□.
The signal indicating the selected block of the signal line up to becomes H. The second patch will be applied to the selected block.
If it is not written to the head (4) of the block selection circuit (13), none of the signals on the signal lines from QE to Q32'J from the block selection circuit (13) will become H, and the logic gate (17
), (18), (19).

(20) A read instruction signal (10) is created by K,
When this signal (10) is valid, the program is read from the first RAM +31 in accordance with the address signal instruction from CPUfil.

If the modification program for the block selected by the decoder (12) is written in the second ROM +41, the signal becomes H in the block selection circuit (13) and 'fi
:, the signal on one signal line from Q to Q3□1 connected to one signal line from P to P3□ becomes H, and logic gates (17), (1a)
.

(19) and (20) cause the instruction signal (11
) is created. On the other hand, encoder (14) Terikala Q
The second ROM (4) indicated by the H signal on the signal line up to
) is created, and when the above signal (II) is valid, the encoder (
According to the instruction of the address signal created in step 14), the second
The modification program is read from ROM +41.

In order to restore the modified state of the program to the previous state, it is sufficient to restore the connection of the jumper wire (21) of the block selection circuit (13) to its original state.

Note that the capacity of the l block and the number of blocks are preferably appropriate for the contents of the modification, and the capacity of the second ROM+41 does not necessarily have to be equal to the capacity of the first ROM+31.

In addition, in the above embodiment, the ROM in which the program is written and the ROM in which the correction program is read are separate, but it is also possible to use a large-capacity R ( Good too.

Needless to say, the present invention can be applied when using a data memory or ROM in which data is written.

〔Effect of the invention〕

As described above, according to the present invention, even if the number of modifications increases, there is no need to increase the number of ROMs used than in the past, and it is easy to restore the previous state, allowing efficient program execution. This has the effect of being able to be corrected.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing the control circuit portion of Fig. 1, and Fig. 3 is an explanation showing the signal line connection method in the block selection circuit of Fig. 2. It is a diagram. In the figure, (1) is the CPU 12) is the program memory of the present invention, (3) is the first ROM, 141i! 2nd ROM, 151 is a control circuit, (12) is a decoder, (
13) is the block selection circuit, (14) is the encoder% (
15) is a signal generation circuit, (17), (18),
(19) and (20) are logic gates. Note that the same reference numerals in each figure indicate the same parts.

Claims (1)

[Claims] A first read-only memory in which a program has been written, and this first read-only memory are divided into multiple blocks for each predetermined number of bytes, and a correction program is applied to each block for blocks in which errors exist in the program. a second read-only memory that has been written into; a decoder that decodes the address signal from the central processing unit and selects a block of the first read-only memory to which the address indicated by the address signal belongs; and a block that is selected by the decoder. If a modification program for the block of the first read-only memory that has been modified is written in the second read-only memory, select the block of the second read-only memory in which the modification program is written. a block selection circuit that generates an address signal of an address belonging to the block of the second read-only memory selected by the block selection circuit; Instructs to read the program from the second read-only memory when the block selection output signal exists, and when the output signal does not exist, the first
A program memory circuit comprising logic circuitry for directing reading of a program from a read-only memory.