JPS6234260A - Access system for nonvolatile memory - Google Patents

Abstract

PURPOSE:To attain the correction in a reading mode of a nonvolatile memory by dividing a CPU and the inside of a memory into plural blocks of nonvolatile memories and writing the same data to these memories. CONSTITUTION:When data are written to a nonvolatile memory 13, a CPU 10 writes the same data to the relatively equal addresses of blocks 1-3. In a reading mode of the memory 13, the data on the relatively equal addresses of blocks 1-3 are read out and these three data are compared with each other for decision of the stored data. Therefore it is possible to presume the correct data obtained immediately before and after the writing process and then to correct the data of all blocks to the correct ones even if the unstable data is already written to either one of blocks of the nonvolatile memories.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a non-volatile memory access method for reading and writing from a writable non-volatile memory. [Prior Art] The recent development of electronic technology is remarkable. There is, especially I
BACKGROUND ART Due to the high integration of C and memory, extremely low cost and high performance electronic devices 1 such as personal computers, word processors, printers, etc. have become available.

On the other hand, along with this, these electronic devices are becoming widespread in various fields, and the way they are used is becoming extremely diverse depending on the usage patterns of each user.

Therefore, a variety of functions are condensed into one electronic device, and each user must select the desired function operation method from among these various functions through complicated operations before starting the actual operation. Many devices designed to do this are also becoming popular.

Therefore, a so-called EEFROM (elect) is installed inside the device.
ricErasable Prograsable
It has a non-volatile memory such as Reed 0nly Me+5ory) and stores various operating parameters of the device (e.g. printer print character pitch, etc.) in the memory, simplifying operator operations after power is turned on. Equipment has also become a reality. However, in the case of conventional devices of this type, if the operator turns off the power to the device at a time when the microprocessor or the like happens to be rewriting the contents of a certain address in this nonvolatile memory, the The problem was that the contents of the address were not rewritten correctly, resulting in completely different data, and as a result, when the power was turned on afterwards, the device started operating in a completely different operating mode.

[Problems to be solved by the invention] The present invention has been made in view of the above-mentioned conventional drawbacks.
For example, an object of the present invention is to provide a nonvolatile memory access method that makes it possible to restore or update the memory even if the contents of the memory are destroyed due to power interruption during writing to the nonvolatile memory.

[Means for solving the problem J As a means to solve this problem, for example, the nonvolatile memory access method of the embodiment shown in FIG. A divided non-volatile memory 13 is provided.

[Operation J] In the configuration shown in FIG. 1, when writing data to the nonvolatile memory 13, the CPU 10 writes the same data to relatively equal addresses of blocks 1 to 3, and when reading from the nonvolatile memory 13, the CPU 10 writes the same data to the relatively equal addresses of the blocks 1 to 3. The data at relatively equal addresses of ~3 are read out, and the three data are compared to determine the stored data.

[Examples] Examples of the present invention will be described in detail below with reference to the accompanying drawings.

[Description of a device with a built-in nonvolatile memory and the data structure of the nonvolatile memory (Fig. 1)] Fig. 1 is a block diagram showing a part of the structure of an electronic device having a nonvolatile memory according to an embodiment of the present invention. It is.

CPU10 is a CPU such as a microprocessor, for example,
It controls the operation of the entire device, and the data bus 14
Data is exchanged with various memories and I10 devices via.

ROMI 1 is a read-only memory that stores control programs for CPU 10 and various fixed tables, etc., and RAM 12 is a rewrite memory that temporarily stores various data and reads them at any time when CPU 10 operates. It is a so-called volatile memory whose contents are destroyed when the device's power is cut off.

The nonvolatile memory 13 is a memory for storing parameters, semi-fixed tables, etc. that determine the operating state and procedure of the device, and its contents can be retained even if the power of the device is cut off. So-called EEFROM, NVRA
M(Man Volatile Random Acc
This type of non-volatile memory includes an element called essMemory (EssMemory), a battery-backed RAM, and the like.

In this embodiment, the number of bytes of all information to be stored in the non-volatile memory 13 is N bytes, but the non-volatile memory 13 has 3N bytes, which is three times that number for an 8-bit memory.
(address 0 to address 3N-1).

Its internal structure is block 1 (address 0 to address N-
1), block 2 (address N le address 2N-1),
It is divided into blocks 3 (addresses 2N to 3N-1), and in this embodiment, normally blocks 1, 2.3 store exactly the same data.

[Explanation of data writing operation to non-volatile memory (FIG. 2)] FIG. 2 shows a flowchart of a program when the CPU 10 stored in the ROMII writes certain data to the non-volatile memory 13.

First, in step S20, desired data is written to the address A of block 1, and then in steps S21 and S22, the address (N +
A) and the address (2N+A) of block 3, that is, when CPU10 writes a certain type of data to the nonvolatile memory 13, the same data is written to address (2N+A) of block 3.
Write to the same relative address position in each block in three steps.

Therefore, if the power of the device is cut off during one of the write steps, the data in the block being written may be undefined, but the data in the other two blocks may be written incorrectly. Or, the correct data before being rewritten still remains.

[Explanation of the relationship between power cutoff timing and data (Figure 2)
(FIG. 3)] FIG. 3 is a diagram showing the relationship between power cutoff timing and data in each block.

Assuming that data is always written to the nonvolatile memory 13 in the order shown in FIG. 2, write step l (corresponding to step 320 in FIG. 3) is performed as shown in FIG.
If a power cut-off or the like occurs, the data in block 1 becomes undefined, but the contents of relatively equal addresses in blocks 2 and 3 remain the original old data. Similarly, step 2 (
When the power is cut off in step S21 (corresponding to step S21 in FIG. 3), the data in block 2 becomes undefined, but block 1 becomes the newly updated data and block 3 becomes the original data. Similarly, in step 3, the data in block 3 becomes undefined, but blocks 1.2 are considered to have already been updated with new data.

[Explanation of read operation of non-volatile memory (Fig. 1) (Fig. 3) (Fig. 4)] Fig. 4 shows a flowchart of a program in which the CPU stored in the ROM II reads certain data from the non-volatile memory 13. First, in step S40, data is read from address A of block l of nonvolatile memory 13 and stored in Di of RAM 12, and this data is stored in Dl.
shall be. Subsequently, in step 541, data is similarly read from the address (N0A) of block 2 and stored in D2 of the RAM 12, and this data is designated as D2. Step S4
2, data is read from address (2N+A) of block 3 and stored in D3 of RAM 12, and this data is stored in D3.
shall be.

In step S43, the aforementioned data DI and D2 are compared, and if they are equal, the process proceeds to step S44. In step S44, D2 and D3 are compared, and if they are equal, the process proceeds to step S45.

At this time, since there is no abnormality in the contents of the nonvolatile memory 13, Dl is adopted as the correct data.

If D2 and D3 are not equal in step S44, the process advances to step 546. In this case, write step 3 in Figure 3.
Since it is thought that a power outage etc. has occurred in block 3, new data D1 of block l is adopted as the correct data and
Write N Di into the address (2N+A) (Step 5
47).

If Dl and D2 are equal in step S43, step S4
In this case, it is considered that a power outage or the like occurred in writing step 1 in FIG. 3, so D2 is adopted as the correct data, and D2 is written to address A of block 1 in step S50.

If it is determined that D2 and D3 are different in partial step 348, then the data in block 1, block 2, and block 3 are not equal. It is believed that this occurred. Therefore, in step S51, the new data Dl of block 1 is adopted as the correct data, and the address of block 2 (N+A
), and in step S53, Dl is written to address (2N+A) of block 3.

With the above reading and modification algorithm, even if undefined data is written to any block of non-volatile memory, the correct data immediately before or after writing can be estimated, and all blocks can be modified to that data. You can keep it.

The means for realizing the present invention is not limited to the embodiments described above, and similar effects can be obtained with other configurations.

For example, the order of writing and reading blocks is not limited to this embodiment, and the nonvolatile memory may be divided into not only three blocks but four, five, or more blocks, and reading from each block may be performed. It is also possible to estimate the correct data from the data obtained using a majority vote method.

Although this embodiment describes the occurrence of an abnormality due to a power cut, the present invention is not limited to this, and it is of course applicable to cases where abnormal writing occurs due to noise or the like, for example.

[Effect of the Invention J As described above, according to the present invention, even if abnormal data is written during a write operation of a nonvolatile memory, it is possible to correct it when reading from the nonvolatile memory. be.

[Brief explanation of drawings]

Figure NIJ1 is a block diagram showing the internal structure of the nonvolatile memory of this embodiment and a part of an electronic device having nonvolatile memory, Figure 2 is a flowchart for writing data to the nonvolatile memory in this embodiment, and Figure 3 is a FIG. 4 is a flowchart for reading data from the non-volatile memory in this embodiment, which is a diagram showing how data in the non-volatile memory is classified when the power is cut off during a write operation. In the figure, 10-CPU, 11・ROM, 12...
RAM, 13... non-volatile memory, 14... data bus. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] The memory space is divided into a plurality of areas, the same information is stored in each of the plurality of areas, and the stored information is estimated by comparing the plurality of pieces of information read from each of the plurality of areas. A non-volatile memory access method featuring: