JPS61288191A - Electronic timepiece - Google Patents

Abstract

PURPOSE:To permit the easy and quick test of load compensation without circuitry increase by setting an electronic timepiece at a quick feed feed in order to test a load compensating circuit of a motor. CONSTITUTION:A mode switch TS of a quick feed control circuit 11 is normally off and a control signal PX is at an H level. A quick feed selecting circuit 3 outputs the frequency divided signal f1 of the normal signal from an oscillation circuit 2 as a selection signal PS. A succeeding frequency dividing circuit 4 which receives the signal PS as the input thereto divided down said signal and outputs a frequency divided signal f4. A motor driving signal PD, detection timing signal PP and, if a motor M is stopped, a motor run correction pulse signal PH are outputted from a driving circuit 9. The signal PX outputs the H level only when a section signal PC arrives if the switch TS is turned on to test the motor. The signal PD, signal PP and signal PH are outputted in the same manner as in the normal state as the signal to be outputted from the circuit 9 in the quick feed mode as well. The test time is therefore reduced while the test conditions for the motor M are correctly maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic timepiece equipped with a motor rotation compensation function.

[Conventional technology]

Conventionally, many electronic watches with a motor rotation compensation function have been commercialized.For example, as shown in Japanese Patent Application Laid-Open No. 59-12380, a motor drive signal is output to drive the motor, and then a motor rotation detection signal is used to drive the motor. It was detected whether the motor was rotating normally or not, and if the motor was not rotating normally, a rotation correction pulse signal was outputted to drive the motor.

[Problem that the invention seeks to solve]

In the aforementioned circuit with a load compensation function, it is necessary to test the load compensation conditions based on the combination conditions with the motor, but testing using drive pulses output every second takes time, and In a method in which a test signal higher than the frequency of the crystal oscillator is input from an oscillator instead of a crystal oscillator, the pulse width of all signals such as vibration signals, detection signals, and rotation correction pulses becomes narrower, which makes it difficult to match the actual driving conditions. The drawback was that no tests were conducted.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic timepiece that solves the above-mentioned conventional problems and allows efficient testing of the load compensation function.

[Failure to solve the problem]

In order to achieve the above object, the present invention has a basic structure. That is, a fast-forward signal switching circuit that controls the operation of the frequency dividing circuit to switch and output a normal signal and a fast-forward signal, and a section signal that includes a section in which the drive pulses and correction pulses output from the pulse motor drive circuit are present are generated. A section signal generating circuit is provided, and the fast forward signal switching circuit is controlled by the section signal so that the section signal generating section returns to the normal mode in the fast forward operation mode of the electronic timepiece.

[Effect]

With the above configuration, in the fast-forward operation mode of the electronic clock, the drive pulse and correction pulse are output with the normal pulse width and timing, and the areas other than that section are accelerated by the fast-forward signal, and then the drive pulse and correction pulse are output. This will shorten the time it takes to arrive.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a circuit block diagram of the electronic timepiece of the present invention,
FIG. 2 is a diagram of main voltage waveforms.

Reference numeral 1 denotes an oscillation circuit, and 2 a pre-stage frequency dividing circuit, which receives the oscillation signal from the oscillation circuit 1, performs a frequency dividing operation, and outputs frequency divided signals f1, f2, and f3.

Reference numeral 6 designates a fast-forward switching circuit, the input end A of which receives the frequency-divided signal f1, which is a normal signal from the previous-stage frequency divider circuit 2, and the input end B receives the frequency-divided signal f2, which is a fast-forward signal. is input, and the control signal PX output from the NAND gate 12 is input to the control terminal C, and when the control signal PX is at H level, the frequency-divided signal f input to the input terminal A is input to the control terminal C. It is output as a selection signal PS, and when the control signal PX is at L level, it is controlled so that the frequency-divided signal f2 input to the input terminal B is output as the selection signal Ps.

Reference numeral 4 designates a rear-stage frequency dividing circuit, which performs frequency dividing operation by inputting the selection signal PS outputted from the fast-forward switching circuit 6;
A frequency-divided signal f of Hz is output.

5 is a drive signal generating circuit, which receives frequency-divided signals f8 . f, as input, the second
The motor drive signal PD is output as shown in Figure (A).

Reference numeral 6 denotes a correction signal generating circuit, which receives branch signals f3 and f4 as input, and whose output is controlled by a rotation detection signal PK from a rotation detection circuit 10, which will be described later.The rotation detection signal PK is as shown in FIG. When at H level, the motor rotation correction pulse signal PH shown in FIG. 2 (a) is output.

7 is a detection signal generation circuit, which generates the motor drive signal PD.
After outputting the detection timing signal PP to the rotation detection circuit 10 for detecting the rotation of the motor M, the detection timing signal PP is sent to the rotation detection circuit 10 in FIG.
The output is as shown in .

8 is a section signal generation circuit, which generates the motor drive signal PD.
And only in the section where the motor rotation correction pulse signal PH exists, the section signal PC is output as shown in FIG. 2 (b).

Reference numeral 9 denotes a drive circuit, which inputs the motor drive signal PD from the drive signal generation circuit 5, correction signal generation circuit 6, and detection signal generation circuit 7, motor rotation correction pulse signal PH1, and detection timing signal PP; The signals shown in FIG. 2 (a) are supplied to

10 is a rotation detection circuit, and the detection timing signal P
This is a circuit that receives P as an input and detects the rotation of the motor M, and outputs a rotation detection signal PK of L level when the motor M rotates normally, and an H level when the motor M does not rotate normally. .

Reference numeral 11 denotes a fast-forward control circuit, which is composed of a mode switch TS-NAND gate 12 that operates in conjunction with an external operating member.

In the normal mode, the mode switch TS is in the OFF state, and the mode signal PM output from the mode switch TS is at L level. When entering the fast forward mode, the mode switch TS is turned on and the mode signal PM is set to an H level signal. The mode signal PM is input to one input terminal of the NAND gate 12, the section signal PC is input to the other input terminal, and the control signal PX is output from the output terminal. The control signal P
X outputs a mode when the mode switch TS is off,
Also, when the mode switch TS is ON, the mode signal PM is H.
When the level is H only when the section signal PC arrives.
Outputs a level signal.

Next, the operation of the electronic timepiece with the above configuration will be explained.

Normally, the mode switch TS of the fast-forward control circuit 11 is in the OFF state, so the control signal PX is at H level, and the fast-forward switching circuit 3 receives the oscillation signal from the oscillation circuit 1 as an input stage and performs a frequency dividing operation. The frequency division signal f, which is a normal signal from the frequency division circuit 2, is outputted as a selection signal PS, and the subsequent stage frequency division circuit 4 receives the selection signal PS as input, divides the frequency, and outputs a frequency division signal f4. Therefore, as shown in FIG. 2(a), the drive circuit 9 outputs a motor drive signal PD.
, the detection timing signal PP and the motor rotation correction pulse signal PH are output every second when the motor M is not rotating, and the motor is driven every second.

Next, when the mode switch TS is turned on to perform the test, the control signal PX outputs an H level only when the section signal PC arrives, as shown in FIG. 2 (b). That is, the fast-forward switching circuit 6 outputs the frequency-divided signal f2, which is a fast-forward signal, as the selection signal PS, and only when the section signal PC arrives, the frequency-divided signal f1, which is a normal signal, is output as the selection signal PS. Therefore, even in the fast forward mode, the signal output from the drive circuit 9 is the same as the motor drive signal P as shown in FIG. 2(A).
D, detection timing signal PP, and motor rotation correction pulse signal PH are output in the same manner as in the normal state. That is, in the fast forward mode, the section where the section signal PC does not exist as shown in FIG.
In order to return to the normal state shown in , the overall feed speed increases and the conditions of each signal supplied to motor M do not change, so it is possible to shorten the test time while maintaining the correct test conditions for motor M. becomes.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, by setting the fast-forward mode to test the load compensation circuit of the motor, the signal for driving the motor and the signal for rotation detection can be changed to the normal pulse width. This has a great effect on providing an electronic clock that can easily perform load compensation tests in a short period of time without adding any additional circuitry by maintaining the cycle and outputting the cycle at a cycle earlier than the normal cycle. there were.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of the electronic timepiece of the present invention, and FIG. 2 is a main voltage waveform diagram. 1... Oscillation circuit, 2.4... Frequency dividing circuit, 6... Rapid forward switching circuit, 5... Drive signal creation circuit, 6... ...correction signal creation circuit, 7.
...detection signal generation circuit, 8 ... section signal generation circuit, 9 ... drive circuit, 10 ....
Rotation detection circuit, M...Motor, 11...
・Fast forward control circuit.

Claims (1)

[Claims] In an electronic timepiece that includes an oscillation circuit, a frequency dividing circuit, a pulse motor drive circuit, and a pulse motor, and detects the rotational operation of the pulse motor after the end of driving the pulse motor and performs rotation compensation using a rotation correction pulse, A fast-forward signal switching circuit that controls the operation of the frequency dividing circuit to switch between a normal signal and a fast-forward signal, and generates a section signal that includes a section in which drive pulses and correction pulses output from the pulse motor drive circuit exist. An electronic timepiece, comprising: a section signal generation circuit for generating a section signal, and controlling the fast-forward signal switching circuit with a section signal so that the section signal generation section returns to the normal mode in the fast-forward operation mode of the electronic timepiece.