JPS6363875B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for detecting the rotation of a step motor in a correction drive system for a step motor for an electronic timepiece. Conventionally, a rotation detection method in a corrected drive system for a step motor for an electronic watch has been carried out by detecting, with a voltage detection element, the state of power generation due to vibration of the rotor after application of a step motor drive signal. Specifically, after applying the step motor drive signal,
The voltage detection element is operated for a certain period of time to detect the voltage generated by the vibration of the rotor, and if the voltage level is above a certain value, rotation is detected, and if it is below a certain value, non-rotation is detected. This detection method does not require any external detection element;
Since it can be realized by adding a voltage detection element to a watch LSI, it is a good method for detecting the rotation of a step motor for an electronic watch. However, in recent correction drive systems, the conventional rotation detection method has become insufficient. In particular, it is the timing of detecting rotation. In the conventional correction drive method, correction drive was performed using one type of main drive signal (hereinafter referred to as main drive pulse P ₁ ) and a correction drive signal (hereinafter referred to as correction drive pulse P ₂ ).
In the latest correction drive, as a result of pursuing even lower power consumption, multiple types of main drive pulses _P1 are provided. The pulse width of the main drive pulse P ₁ is approximately 2.44 ms to 3.66 ms in 0.24 ms steps, and there are about six types of main drive pulses P ₁ . To briefly explain this correction drive system, the timepiece always tries to drive a step motor (hereinafter abbreviated as "motor") with the bare minimum of power. For example, now the main drive pulse P ₁ is 3.16m
If the motor stops rotating for some reason, the correction drive pulse P ₂ is immediately applied.
to re-drive. This point is exactly the same as the conventional correction drive method. The difference is that the pulse width of the main drive pulse P ₁ one second after performing correction drive with the correction drive pulse P ₂ becomes 3.16 + 0.24 = 3.40ms, and automatically changes to a pulse width with a margin. do. When the motor stops rotating like this, the pulse width is automatically lengthened to ensure stable motor drive, and when the motor continues to rotate for a certain period of time, the main drive pulse _P1 is changed to save power consumption. Automatically narrows the pulse width and drives the motor. In this way, the latest correction drive system has been improved to automatically find the lowest pulse width that can drive the motor. As described above, the latest correction drive has been improved as a result of pursuing lower power consumption, but the rotation detection method is exactly the same as the conventional correction drive method. As a result, in the latest correction drive system, a problem has arisen in the timing of detecting rotation. That is, in the conventional correction drive system, the main drive pulse _P1 has one type of pulse width of approximately 3.90 ms, and the timing of rotation detection is also one type. The timing of this rotation detection is designed to coincide with the timing at which the peak of the generated voltage due to rotor vibration occurs. The timing at which the peak of the generated voltage generated by rotor vibration occurs varies depending on the pulse width of the main drive pulse _P1 .
In the conventional correction drive method, the main drive pulse
Since P ₁ was one type, the timing of rotation detection could be determined to the optimum value. However, if there are a plurality of main drive pulses P ₁ as in the latest correction drive system, the timing at which the generated voltage generated by the vibration of the rotor is generated changes depending on the pulse width of the main drive pulse P ₁ . However, the timing of rotation detection is the same as in the past, and only one type is available, making it difficult to detect rotation. Since the main drive pulse P ₁ changes, the timing of rotation detection is designed with a certain margin, and rotation/non-rotation detection is approximately 13.6 ms after 10 ms has elapsed from the rise of the main drive pulse P ₁ . Rotation is being detected. Conventionally, the optimal rotation detection timing was set for one type of main drive pulse P ₁ , but this detection period is set for multiple main drive pulses P ₁ , so the detection timing is longer. As a result, more power is consumed for detection, and the timing at which the peak of the detection voltage occurs and the timing at which the rotation is detected are different from each other, leading to the risk of erroneous detection. Therefore, the purpose of the present invention is to provide a plurality of rotation detection timings so as to provide the optimum rotation detection timing corresponding to the main drive pulse _P1 , so that rotation detection can always be performed at the optimum timing, and to ensure stable rotation detection. The objective is to provide a new electronic clock that is motor-driven and has low power consumption. Hereinafter, one embodiment of the present invention will be shown and described in detail. First, before explaining the present invention, a specific rotation detection method will be explained. Figure 1 shows the motor driver section and rotation detection section. 1 and 3 are PMOSFET gates (hereinafter referred to as PTr)
), 2 and 4 are NMOSFET gates (hereinafter referred to as
(abbreviated as NTr) and supplies power to the coil 5 of the motor. 7 and 6 are detection resistors Rs for rotation detection
The voltage generated by the vibration of the rotor is detected by switching the detection transistors 8 and 9. One ends of the detection resistors Rs6 and Rs7 are connected to non-inverting input terminals of voltage detection elements 10 and 11 (here, operational amplifiers), respectively. A reference voltage generation resistor 12 and a reference voltage generating resistor 12 are connected to the inverting input terminals of the voltage detection elements 10 and 11.
A reference voltage V _TH for detection generated at the NMOSFET gate (hereinafter abbreviated as NTr) 13 is connected, and the generation of the reference voltage V _TH and the operation of the voltage detection element are controlled by the signal G.
controlled by The outputs of the voltage detection elements 10 and 11 are connected to a NOR gate (hereinafter abbreviated as NOR) 14, and are connected to NAND gates 15 and 16 (hereinafter referred to as latch 1).
5, 16) is set. The latches 15 and 16 are in a relationship to output a rotation detection signal to a control circuit (not shown). The operation will be explained using the timing chart shown in FIG. The signals shown in FIG. 2 are input to the terminals marked in alphabetical order in FIG. 1. The period T ₁ is the timing at which the main drive pulse P ₁ is applied to the coil 5. At this time, PTr1 and
NTr4 is ON, and PTr3 and NTr2 are OFF. After the motor rotates in section T ₁ , a detection signal for detecting the rotation of the motor is transmitted to detection transistor 8 from section T ₂ .
The signals are input to NTr2 and switched respectively. As a result, the induced voltage induced in the coil 5 by the vibration of the rotor after the application of the main drive pulse _P1 is:
A detection voltage _VRS is generated across the detection resistor Rs6. This detection voltage V _RS is connected to the voltage detection element 11, but since the voltage detection element 11 is not operating at the timing of section _T2 , it is not actually detected. This is because no difference is observed in the detection voltage V _RS between rotation and non-rotation in the interval T ₂ to avoid erroneous detection. In interval _T3 , the switching is performed by the switching signal E, and the voltage detection elements 10 and 11 are connected to the reference voltage by the rotation detection signal G.
NTr8, which generates V _TH , turns ON. As a result,
V _RS and V _TH are detected by voltage detection element 11, and V _RS >
If V _TH , rotation is detected; if V _RS < V _TH , non-rotation is detected.
When rotation is detected, the output of the voltage detection element 11 is
“0” (“0” = V _SS , “1” = V _DD ), and at this moment, the R-S latches 15 and 16 are set, and the R-S latches 15 and 16 are set.
The output H of the -S latches 15 and 16 becomes "1".
(The output of the voltage detection element 10 is connected to the detection resistor Rs7.
As a result, the control circuit (not shown) connected to the outputs H of the R-S latches 15 and ₁₆ is in the "1" state since the output H is "1" _. Prohibits correction drive pulse _P2 and does not output it. In the next section _T5 , the R-S latch 1 is activated by signal I in preparation for motor drive in the next 1 second.
5 and 16. Also, when non-rotation (V _RS < V _TH ) is detected, voltage detection element 11
The output of R-S latch 1 remains “1” and R-S latch 1
5 and 16 remain in the reset state. As a result, the correction drive pulse _P2 in section _T4 turns PTr1 ON.
The relationship is such that the motor is re-driven. In the rotation detection method described above, the timing of the rotation detection signal G is fixed. The problem here is that the timing at which the detection voltage V _RS is generated changes depending on the load. In other words, when the load is light, the rotor rotates quickly, the voltage level of the detection voltage V _RS is high, and the peak of the detection voltage V _RS occurs early, so the rotation is started early in the rotation detection period T ₃ . It will be detected. Conversely, when the load is heavy, the rotor rotation is slow and the voltage level of the detection voltage V _RS is low, causing the detection voltage
The timing at which the V _RS peak occurs is also late. As a result, the timing at which rotation is detected is around the end of section _T3 . In the worst case, a peak of the detection voltage V _RS may occur after the end of the period T ₃ , the rotation may be detected as non-rotation, and the motor may be driven again by the corrected drive pulse P ₂ . The present invention aims at detecting voltage due to this difference in load.
The idea is to pay attention to the timing at which V _RS occurs and automatically change the timing at which rotation detection is performed to the optimum timing. In other words, light load and heavy load correspond to narrow and wide pulse widths of the main drive pulse _P1 , respectively, so rotation detection is performed in the optimal rotation detection interval corresponding to the pulse width of the main drive pulse _P1 . This is how it was done. FIG. 3 shows a block diagram showing one embodiment of the present invention. 17 is an oscillation circuit that generates a reference signal for the clock. A frequency dividing circuit 18 divides the frequency of the oscillation signal generated by the oscillation circuit 17 and supplies each circuit with a frequency necessary for circuit operation. 19 is an up/down counter 20 for selecting the pulse width of the main drive pulse _P1 and the timing of circuit detection.
(hereinafter abbreviated as up/down counter) is a counter circuit that generates a down signal. 21 is up/
This is a main drive pulse P ₁ generation circuit that generates the main drive pulse P ₁ based on the signal from the down counter 20.
Reference numeral 22 denotes a rotation detection signal generation circuit that generates a rotation detection signal based on the signal from the up/down counter 20. 23 is a correction drive pulse P ₂ generation circuit that generates a correction drive pulse P ₂ . 24 is a switching signal generation circuit that generates a switching signal for rotation detection. Reference numeral 25 denotes a motor drive section including a drive circuit for driving the motor and a detection circuit for detecting rotation/non-rotation. 27, 28 are
AND gates 26 and 29 are NOR gates. The up/down counter 20 is in hexadecimal format, for example.
As an up/down counter, it is assumed that the bit output contents of the up/down counter 20 are "0\", "0\", and "0\". The main drive pulse P ₁ generation circuit 21 generates a signal from the bit output “0\” “0\” “0\” of the up/down counter 20.
For example, it is configured to generate a main drive pulse _P1 of 2.44 ms. The rotation detection signal generation circuit 22 is
Bit output of up/down counter 20 “0\” “0\”
From “0\”, the optimum rotation detection signal is generated for the main drive pulse P ₁ 2.44ms. As a result, the main drive pulse P ₁ 2.44ms generated by the main drive pulse P ₁ generation circuit 21 is
The signal is inputted to the motor drive section 25 via 9 to rotate the motor. After applying the main drive pulse P ₁ for 2.44 ms, the motor drive section 25 detects rotation or non-rotation of the motor based on the switching signal from the switching signal generation circuit 24 and the detection signal from the rotation detection signal generation circuit 22. As a result of the detection, if it is non-rotating, the output of the motor drive section 25, signal line a, becomes "1". As a result, P ₂ generated in the correction drive pulse P ₂ generation circuit 23 quickly re-drives the motor via AND 28 and NOR 29, and at the same time
This relationship causes the counter 20 to count up. As a result of counting up, up/down counter 20
The bit output is “1”, “0”, and “0”. The main drive pulse is set so that the pulse width of the main drive pulse _P1 becomes wider as the weight of the bit output of the up/down counter 20 increases.
The _P1 generation circuit 21 is configured in advance. Also, if rotation is detected, the motor drive unit 25
The output of is “0\”, and the correction drive pulse P ₂ generated by the correction drive pulse P ₂ generation circuit 23 is AND2
8 and prohibits the up/down counter 20 from counting up. As a result, there is no change in the contents of the up/down counter 20, so the next main drive pulse P ₁ in the rotating state
The pulse width remains unchanged. Further, the counter circuit 19 further divides the frequency of the signal from the frequency dividing circuit 18, and performs up/down processing at a period of, for example, 80 seconds.
Generates a down count signal for the counter 20,
The relationship is such that the up/down counter 20 is counted down. As a result, the pulse width of the main drive pulse _P1 is narrowed by one step every 80 seconds. The relationship between each circuit has been explained above. The main feature of the present invention is that the up/down counter 2
The point is that the rotation detection signal is changed by the 0 bit output. If the pulse width of the main drive pulse P ₁ is narrow, the timing at which the detection voltage V _RS is generated is delayed, and if the pulse width of the main drive pulse P ₁ is wide, the detection voltage V _RS
The timing of occurrence will be earlier. From this,
By changing the timing of the rotation detection signal depending on the pulse width of the main drive pulse _P1 , rotation detection can be performed at the optimal detection timing. Specifically, when the pulse width of the main drive pulse _P1 is narrow, the timing of rotation detection is delayed.
Also, when the main drive pulse _P1 has a wide pulse width,
By speeding up the timing of rotation detection, good rotation detection can be expected. A more detailed example of changing the pulse width of the main drive pulse _P1 and the rotation detection signal by the bit output of the up/down counter will be described with reference to FIG. 4. 20 is a hexadecimal up/down counter, and its bit output controls a main drive pulse generation circuit 21 and a rotation detection signal generation circuit 22. The main drive pulse generation circuit 21 is a hexadecimal up/down
2.44, 2.68, 2.92, depending on the bit output of counter 20,
Generates six types of main drive pulses of 3.16, 3.40, and 3.66ms. The rotation detection signal generation circuit 22 has a hexadecimal up/down
The configuration is such that three types of rotation detection signals are generated based on the bit output of the counter 20. The specific operations of the main drive pulse P ₁ generation circuit 21 and the rotation detection signal 22 inside the broken lines will be described. The specific circuit of the hexadecimal up/down counter is a common circuit, so a description thereof will be omitted. 30 is a NAND gate (hereinafter abbreviated as NAND), and the 1st bit of the hexadecimal up/down counter (hereinafter b ₁
from the frequency divider circuit (not shown) at the output b ₁ of
It controls the 2048Hz signal. 31 is
It is a NAND/OR gate, and outputs ₂ and b3 of the 2nd bit (hereinafter abbreviated as b2) and 3rd bit (hereinafter abbreviated as _b3 ) of the hexadecimal ^up /down counter ₂₀ are connected to a frequency dividing circuit ( _b2 is an inverter). 23, so it becomes ₂ )
It controls the 1024Hz signal from. 32 is a NAND/OR gate, hexadecimal up/
512 of the frequency dividing circuit using the b ₂ and b ₃ outputs of the down counter 20
It controls the Hz signal. NAND30, NAND・
The outputs of OR31 and 32 are connected to the gate of NAND gate 33. NAND33 is the 256Hz signal from the frequency dividing circuit, NAND30, NAND・OR3
D Type F/F34 (below) with output of 1,32
DF/F) clock signal is generated. The DF/F 34 is operated by the 1 Hz signal from the frequency dividing circuit input to the Data terminal and the clock signal from the NAND 33. NOR gate 35 is DF/F34
Data signal and output once per second in hexadecimal
A main drive pulse that changes depending on the bit output of the up/down counter 20 is generated and output to a motor drive section (not shown). Next, the connection relationship of the rotation detection signal generation circuit 22 will be explained. 36, 38, 40 are NOR (hereinafter abbreviated as NOR)
It is a gate, and 37, 39, 41 are NOR/AND
(hereinafter abbreviated as NOR/AND) gates, and each gate controls the signal from the frequency dividing circuit using the b ₂ and b ₃ signals of the hexadecimal up/down counter 20. NOR36 and NOR・AND37 are hexadecimal up/
64 from the frequency divider circuit with the _b3 signal of down counter 20
Control Hz signal. NOR38 and NOR/AND39 are hexadecimal up/
32 from the frequency divider circuit with the _b3 signal of the down counter 20
Control Hz signal. NOR40 and NOR・AND41 are hexadecimal up/
128 from the frequency divider circuit with the _b2 signal of down counter 20
Control Hz signal. The NOR•ANDs 37, 39, and 41 are input to the NAND gate 42. 44 is a latch circuit, and data terminal D and clock terminal C receive a 1Hz signal from a frequency dividing circuit and a 16Hz signal.
Each signal is input. 43 is a NOR gate (hereinafter abbreviated as NOR), and latch circuit 4
4 data terminal and output terminal signals, 1 per second
It generates a 31.25ms pulse once and outputs it to the NAND42. NAND42 is NOR・AND37,39,4
1 output and NOR43 output once per second,
It generates a rotation detection signal that changes depending on the bit output of the hex up/down counter 20, and drives a voltage detection element (not shown) for rotation detection. Next, the operation timings of the main drive pulse _P1 generation circuit 21 and the rotation detection signal generation circuit 22 are shown in FIGS. 5 and 6, respectively, and the operations will be explained. The bit output of hexadecimal up/down counter 20 is b ₁ =
Assuming that the conditions are “0”, b ₂ = “0”, and b ₃ = “0”,
NAND30 of main drive pulse _P1 generation circuit is 2048Hz
Inhibits the signal and outputs “1” to NAND33.
NAND/OR31 inverts the 1024Hz signal and 1024Hz
Output Hz to NAND33. NAND・OR32
prohibits the 512Hz signal and outputs “1” to NAND33. As a result, NAND33 takes 256Hz and 1024Hz and becomes the clock signal of DF/F34. Assuming that DF/F34 operates at the falling edge of the clock signal, the falling timing of the 256Hz/1024Hz signal is 2.44ms from the second, so NOR35 operates at 2.44ms.
The main drive pulse _P1 is generated. Also, the bit output of the hexadecimal up/down counter is b ₁ =
If "0", b ₂ = "1", and b ₃ = "0", the main drive pulse generation circuit 21 generates a main drive pulse of 2.92 ms. NAND30 prohibits 2048Hz signal and sets “1”
Output to NAND33. NAND・OR31 is
Inverts the 1024Hz signal and outputs 1024Hz to NAND33. NAND/OR32 inverts the 512Hz signal and outputs it to NAND33. As a result, NAND33 is 256Hz, 512Hz, 1024
Hz and becomes the DF/F34 clock signal. Since the DF/F 34 operates at falling timings of 256 Hz, 512 Hz, and 1024 Hz (2.92 ms from the second), the NOR 35 generates a main drive pulse of 2.92 ms. In this way, the main drive pulse P ₁ is hexadecimal up/down
It changes depending on the bit output of the counter 20. In the embodiment shown in Figure 4, the main drive pulse is determined by the bit output of the hexadecimal up/down counter 20.
It changes like 1.

[Table] According to the present invention, as the main drive pulse _P1 changes, the rotation detection signal also changes. In the embodiment shown in FIG. 4, the b ₂ and b ₃ output signals of the hexadecimal up/down counter 20 are used to change the rotation detection signal. The bit output of the hexadecimal up/down counter 20 is b ₂ =
In the state of “0” and b ₃ = “0”, NOR・AND37
outputs 64Hz to NAND42. NOR/AND39 outputs 32Hz to NAND42. NOR・AND41 outputs 128Hz to NAND42. The latch circuit 44 and NOR43 circuit are
A signal that is "1" is output to the NAND 42 for 31.25 ms from the timing of the second on the hour every second. As a result, NAND42 is 43.32Hz.
Since it takes 128Hz and 64Hz, the output is 19.5 from the second.
After the lapse of ms, a rotation detection signal that becomes "0" for 3.9 ms is generated. The bit output of the hexadecimal up/down counter 20 is b ₂ =
In the state of “1”, b ₃ = “0\”, NOR・AND37,
Each gate of 39 and 41 has 64Hz, 32Hz, and 128Hz.
Output to NAND42. As a result, the rotation detection signal becomes a signal for 3.9 ms after 15.6 ms has elapsed since the second. Also, the bit output of the hexadecimal up/down counter 20 is b ₂
The rotation detection signal in the state of = “0\” and b ₃ = “1” is the same circuit operation, and the rotation detection signal is 3.9 m after 11.7 ms has elapsed from the second.
It becomes a signal between s. Table 2 shows the relationship between changes in the rotation detection signal and changes in the main drive pulse _P1 .

[Table] As shown in Table 2, in this embodiment, when the pulse width of the main drive pulse _P1 is narrow, the detection timing of the rotation detection signal is delayed. Furthermore, if the pulse width of the main drive pulse _P1 is wide, the detection timing is made earlier. That is, if the pulse width of the main drive pulse _P1 is narrow, the rotation speed of the motor rotor will be slow, and the timing of generation of the detection signal _VRS will be delayed, so the timing of rotation detection is delayed. Conversely, if the pulse width of the main drive pulse _P1 is wide, the rotational speed of the rotor becomes faster, so the timing of rotation detection is accelerated accordingly. In this way, the timing of rotation detection can be optimally set according to the driving force of the main drive pulse _P1 . At the same time, rotation has been conventionally detected by operating a voltage detection element for 10-odd milliseconds.
Since the detection timing can be set to the optimal one,
The time for operating the voltage detection element can be shortened (3.9 ms in this embodiment), which has the effect of reducing power consumption for detection. As described above, according to the present invention, it is possible to optimize the timing of rotation detection and reduce power consumption for detection as the driving force of the correction drive method changes. Note that the relationship between the main drive pulse _P1 and the rotation detection signal described in this embodiment is merely an example, and is actually determined through experiments. Further, although one type of rotation detection timing is used for two types of main drive pulses P ₁ , it is also possible to easily use one type of rotation detection signal for one type of main drive pulses P ₁ . In addition, in this embodiment, only the timing of the rotation detection signal was changed and the output timing of the corrected drive pulse _P2 was not changed. However, when setting the optimum rotation detection timing, the output timing of the corrected drive pulse _P2 and the rotation Detection timing may be delayed. To prevent this from happening, the output timing of the corrected drive pulse _P2 may be changed in accordance with the change in the rotation detection signal. In the embodiment used in the explanation, this can be easily achieved by controlling the correction drive pulse _P2 generation circuit with the bit output of the hexadecimal up/down counter. As described above, in the present invention, optimal rotation detection can be performed according to the driving force of the main drive pulse _P1 , so a stable rotation detection method without the risk of false detection is realized, and rotation detection This has the effect of reducing power consumption for.

[Brief explanation of drawings]

Figure 1 is a diagram showing the motor driver section and rotation detection part, Figure 2 is a diagram showing the operation timing of Figure 1, Figure 3 is a diagram showing an embodiment of the present invention, Figure 4
Figure 5 shows a specific example of the main drive pulse _P1 generation circuit and rotation detection signal generation circuit, and Figure 5 shows the main drive pulse.
A diagram showing the operation timing of the _P1 generation circuit, Figure-6
FIG. 3 is a diagram showing the operation timing of the rotation detection signal generation circuit. 1...PMOSFET gate, 2...NMOSFET
Gate, 3... PMOSFET gate, 4...
NMOSFET gate, 5... Coil, 6... Detection resistor Rs, 7... Detection resistor Rs, 8... Detection transistor, 9... Detection transistor, 10... Voltage detection element, 11... Voltage detection element, 12... ...resistance for reference voltage generation, 13...NMOSFET gate,
14...NOR gate, 15...NAND gate,
16...NAND gate, 17...Oscillation circuit, 1
8... Frequency dividing circuit, 19... Counter circuit, 20...
...Up-down counter, 21...Main drive pulse
_P1 generation circuit, 22... Rotation detection signal generation circuit,
23...Correction drive pulse _P2 generation circuit, 24...
Switching signal generation circuit, 25...Motor drive unit, 26...NOR gate, 27...AND gate, 28...AND gate, 29...NOR gate, 30...NAND gate, 31...AND・
OR gate, 32...NAND/OR gate, 33
...NAND gate, 34...D type F/F,
35...NOR gate, 36...NOR gate, 3
7...MOR/AND gate, 38...NOR gate, 39...NOR/AND gate, 40...
NOR gate, 41...NOR/AND gate, 4
2...NAND gate, 43...NOR gate, 4
4...Latch circuit.

Claims (1)

[Claims] 1. A motor drive unit having a detection circuit that detects rotation/non-rotation based on the induced voltage of the step motor;
a rotation detection signal generation circuit that outputs a rotation detection signal for operating the detection circuit; a plurality of main drive signals having different effective power values for driving the step motor; and a correction drive having an effective power value larger than the main drive signal. In electronic clocks with signals,
The rotation detection signal generation circuit is controlled by the output of the selection circuit that selects and outputs the plurality of main drive signals, and the time for outputting the rotation detection signal in response to the main drive signal applied to the step motor is controlled. An electronic clock that features different features.