JPS61287130A - Chip carrier for electronic element - Google Patents
Chip carrier for electronic elementInfo
- Publication number
- JPS61287130A JPS61287130A JP60128514A JP12851485A JPS61287130A JP S61287130 A JPS61287130 A JP S61287130A JP 60128514 A JP60128514 A JP 60128514A JP 12851485 A JP12851485 A JP 12851485A JP S61287130 A JPS61287130 A JP S61287130A
- Authority
- JP
- Japan
- Prior art keywords
- metal substrate
- printed wiring
- wiring board
- recess
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［技術号野］
本発明は、ＩＣパッケージなどのような電子素子の基板
として用いられる電子素子用チップキャリアに関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a chip carrier for an electronic device used as a substrate for an electronic device such as an IC package.
［背景技術Ｊ
ＩＣパッケージなどのような電子素子は、半導体チップ
などの電子部品チップをリードフレームに取り付けた状
態で樹脂封止や気密封止してパフケーノングすることに
よっておこなわれる。そしてこのような電子素子にあっ
て、端子数の増加に伴って電子部品チップを支持するキ
ャリアとしてのり一ド７レームの替わりにプリント配線
板を用いる試みがなされている。[Background Art J Electronic devices such as IC packages are manufactured by attaching an electronic component chip such as a semiconductor chip to a lead frame, sealing it with a resin or hermetic sealing, and performing puff caning. With the increase in the number of terminals in such electronic devices, attempts have been made to use printed wiring boards instead of glue boards as carriers for supporting electronic component chips.
ここにおいて、近時の電子部品チップの高密度化は発熱
を伴い、この熱を逃がす工夫が必要とされる。しかしキ
ャリアとして用いられるプリント配線板は樹脂系のもの
やセラミック系のものを基板として形成されており、熱
の伝導性が悪くて放熱を良好になすことができず、電子
部品チップのキャリアとしてプリント配線板を用いるこ
とについて゛の難点になっているものである。Here, the recent increase in the density of electronic component chips is accompanied by heat generation, and it is necessary to devise ways to dissipate this heat. However, printed wiring boards used as carriers are made of resin or ceramic substrates, which have poor thermal conductivity and cannot dissipate heat well, so they are printed as carriers for electronic component chips. This is a major problem with using wiring boards.
［発明の目的］
本発明は、上記の点に鑑みて為されたものであり、放熱
性に優れた電子素子用チップキャリアを提供することを
目的とするものである。[Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a chip carrier for an electronic device that has excellent heat dissipation properties.
［発明の開示Ｊ
しかして本発明に係る電子素子用チップキャリ７は、金
属基板１の表面を絶縁層２で被覆すると共にこの絶縁層
２の表面に回路導体３を設けて金属ベースのプリント配
線板４を形成し、このプリント配線板４の表面の一部で
絶縁層２及び金属基板１の表層部を切欠して口部６を設
け、この四部６内に電子部品チップ５を実装して成るこ
とを特徴とするものであり、チップキャリアとして用い
るプリント配線板４を放熱性の良好な金属ベースで形成
するようにし、しかも電子部品チップ５を！！［６内に
て直接金属基板１に接触させた状態で金属基板１への伝
熱が良好におこなわれるようにして上記目的を達成した
ものであって、以下本発明を実施例により詳述する。[Disclosure of the Invention J The chip carrier 7 for electronic devices according to the present invention covers the surface of a metal substrate 1 with an insulating layer 2, and provides a circuit conductor 3 on the surface of this insulating layer 2 to form a metal-based printed wiring. A board 4 is formed, a portion of the surface of the insulating layer 2 and the metal substrate 1 is cut out at a part of the surface of the printed wiring board 4 to provide an opening 6, and an electronic component chip 5 is mounted within the four parts 6. The printed wiring board 4 used as a chip carrier is formed of a metal base with good heat dissipation, and the electronic component chip 5 is also formed! ! [6] The above object has been achieved by ensuring good heat transfer to the metal substrate 1 in a state where the metal substrate 1 is in direct contact with the metal substrate 1. .
チップキャリアとして用いる金属ベースのプリント配線
板４は例えば特公昭５６−３７７２０号公報に開示され
る方法などによりて作成することができる。すなわち、
まず１１ｉ１１２図（、）に示すように銅板、銅合金板
、綱−インバーー銅（Ｃｕ−Ｉｎｖ−ＣＵ）合金板、鉄
−ニッケル合金板、４２７０イ板、その他制板、鉄板、
アルミニウム板などで形成される金属基板１に貫通孔１
１を設けて、この金属基板１の表面にプリプレグ１２を
介して＃！箔などの金属箔１３を重ねる。プリプレグ１
２はガラス布などの基材にエポキシ樹脂やポリイミド樹
脂、テフロン等のフッ素樹脂などの樹脂フェスを含浸し
て加熱乾燥することによって作成される。そしてこのよ
うに金属基板１にプリプレグ１２と金属１Ｗ１３とを重
ねて加熱加圧成形をおこなうことによって、プリプレグ
１２中の含浸樹脂を滲出させて第２図（ｂ）のようにこ
の樹ｊ１１４で金属基板１の貫通孔１１を充填させるか
もしくは少な（とも貫通孔１１の内周面をこの樹脂１４
で被覆させる。The metal-based printed wiring board 4 used as a chip carrier can be produced, for example, by the method disclosed in Japanese Patent Publication No. 56-37720. That is,
First, as shown in Figures 11i and 112 (,), copper plates, copper alloy plates, steel-invar-copper (Cu-Inv-CU) alloy plates, iron-nickel alloy plates, 4270I plates, other control plates, iron plates,
A through hole 1 is formed in a metal substrate 1 made of an aluminum plate or the like.
1 is provided on the surface of the metal substrate 1 via the prepreg 12. A metal foil 13 such as foil is layered. Prepreg 1
No. 2 is produced by impregnating a base material such as glass cloth with a resin face such as epoxy resin, polyimide resin, or fluororesin such as Teflon, and heating and drying it. By superimposing the prepreg 12 and the metal 1W13 on the metal substrate 1 and performing heat and pressure molding in this way, the impregnated resin in the prepreg 12 is oozed out and the metal is formed using the wood j114 as shown in FIG. 2(b). Fill the through hole 11 of the substrate 1 or fill it with a small amount (in both cases, fill the inner peripheral surface of the through hole 11 with this resin 14.
Cover with
このようにして、プリプレグ１２の含浸樹脂が硬化する
ことによって形成される絶縁層２によって金属箔１３を
金属基板１の表面に貼り付けるようにするものであり、
こののち貫通孔１１の径よりも小さい径で樹脂１４と絶
縁層２と金属箔１３とに貫通して孔加工を施すことによ
って、第２図（ｅ）のようにスルーホール１５を形成さ
せる。このスルーホール１５はその内周面が＠ｆｉ１４
で被覆さ厩、金属基板１に対する絶縁性を確保すること
ができるものである。そして金属Ｗｉ１３にエツチング
などを施すことによって常法に従って回路形成をし、第
２図（ｄ）のように回路導体３を１８１層２の表面に設
けると共にスルーホール１５にスルーホールメッキ１６
などを施すことによって、金属基板１をベースとしたプ
リント配線板４を作成するものである。尚、このプリン
ト配線板４にあって、絶縁層２を形成するプリプレグ１
２としてはＦＲ−４程度の耐熱がラスエポキシを用いる
ようにするのが好ましいが、その他耐熱熱硬化性樹脂や
耐熱熱可塑性樹脂を金属基板１の表面に塗布することに
よって絶縁層２を形成させることもできる。In this way, the metal foil 13 is attached to the surface of the metal substrate 1 by the insulating layer 2 formed by hardening the impregnated resin of the prepreg 12,
Thereafter, a hole is drilled through the resin 14, the insulating layer 2, and the metal foil 13 with a diameter smaller than that of the through hole 11, thereby forming a through hole 15 as shown in FIG. 2(e). The inner peripheral surface of this through hole 15 is @fi14
It is possible to ensure insulation with respect to the metal substrate 1 coated with the metal substrate 1. Then, a circuit is formed by etching the metal Wi 13 in accordance with a conventional method, and the circuit conductor 3 is provided on the surface of the 181 layer 2 as shown in FIG.
By performing the above steps, a printed wiring board 4 based on the metal substrate 1 is created. In addition, in this printed wiring board 4, the prepreg 1 forming the insulating layer 2 is
As for 2, it is preferable to use a lath epoxy having a heat resistance of about FR-4, but the insulating layer 2 can also be formed by applying a heat-resistant thermosetting resin or a heat-resistant thermoplastic resin to the surface of the metal substrate 1. You can also do that.
そしてこのように形成したプリント配線板４にあって、
半導体チップなどの電子部品チップ５を実装すべき位置
において、プリント配線板４の表面の一部に座ぐり加工
を施して絶縁層２及び金属基板１の表層部を切削し、凹
部６をプリント配線板４の表面に設ける。二の凹部６は
絶縁層２が除去されると共に金属基板１の表層部が掘削
されで形成されることになるために、半導体チップなど
の電子部品チップ５を収めることができる程度の深さに
形成することができ、また凹部６の底部において金属基
板１が露出することになる。そして次いでこの凹部６内
に電子部品チップ５を搭載して電子部品チップ５の裏面
を凹部６の底部においで金属基板１に接触させ、第１図
に示すようにワイヤーボンディング１７などを電子部品
子ツブ５と回路導体３との闇に施すことによって、プリ
ント配線板４への電子部品チップ５の実装をおこなうも
のである。このようにしてプリント配＃Ｉ＠４をチップ
キャリアとして電子部品チップ５を保持させ−１そして
これをパフケージングすることによって電子素子として
仕上げるものである。ここで第１図に示すものはＰＧＡ
（ピングリット ７レー）型の電子素子として形成され
るようにしたものであり、このものではプリント配線板
４に設けた各スルーホール１５．１５・・・に端子ピン
１８，１８・・・を下方乃至上方に突出させるように取
り付けるようにしである、このものにおいで、スルーホ
ール１５は内周面が絶縁被覆された状態にあるために、
金属基板１に対する絶縁を確保して端子ピン１８の取り
付けをおこなうことができるものである。And in the printed wiring board 4 formed in this way,
At a position where an electronic component chip 5 such as a semiconductor chip is to be mounted, a part of the surface of the printed wiring board 4 is counterbored to cut the surface layer of the insulating layer 2 and the metal substrate 1, and the recess 6 is used for printed wiring. Provided on the surface of the plate 4. The second recess 6 is formed by removing the insulating layer 2 and excavating the surface layer of the metal substrate 1, so that it is deep enough to accommodate the electronic component chip 5 such as a semiconductor chip. The metal substrate 1 will be exposed at the bottom of the recess 6. Then, the electronic component chip 5 is mounted in the recess 6, the back surface of the electronic component chip 5 is brought into contact with the metal substrate 1 at the bottom of the recess 6, and wire bonding 17 etc. are connected to the electronic component as shown in FIG. The electronic component chip 5 is mounted on the printed wiring board 4 by applying it between the knob 5 and the circuit conductor 3. In this way, the printed wiring board #I@4 is used as a chip carrier to hold the electronic component chip 5-1, and is finished as an electronic device by puff caging. Here, what is shown in Figure 1 is the PGA
(pin grid 7-ray) type electronic element, in which terminal pins 18, 18, etc. are inserted into each through hole 15, 15,... provided in the printed wiring board 4. In this case, the through hole 15 is installed so as to protrude downward or upward, and since the inner peripheral surface of the through hole 15 is coated with insulation,
The terminal pins 18 can be attached while ensuring insulation from the metal substrate 1.
またこのようにＰＧＡ型の電子素子として形成する他、
ＬＣＣ（リードレスチップキャリア）型の電子素子とし
て形成することもできる。In addition to forming it as a PGA type electronic element in this way,
It can also be formed as an LCC (leadless chip carrier) type electronic device.
上記のように金属基板１をベースとしたプリン）配線板
４に電子部品チップ５を取り付けて電子素子を形成する
ようにしたものにあって、金属基板１は熱の良導体であ
って放熱性に優れ、電子部品チップ５からの発熱の放散
を良好におこなうことができるものであり、しかも電子
部品チップ５は熱伝導性が良好でない絶縁層２を除去し
さらに金属基板１の表層部を掘削しで形成した口部６内
に実装されていて、電子部品チップ５を金属基板１に直
接接触させることができると共に電子部品チップ５を広
い面積で金属基板１と対向させることができるために、
電子部品チップ５の熱は効果的に直接金属基板１に伝達
されて放熱されることになり、電子部品チップ５からの
放熱を効率良くおこなうことがで終ることになる。この
ように電子部品チップ５からの発熱を良好に放熱するこ
とができるために電子部品チップ５の高密度化が可能に
なるものである。As described above, an electronic component chip 5 is attached to a wiring board 4 based on a metal substrate 1 to form an electronic element, and the metal substrate 1 is a good conductor of heat and has good heat dissipation properties. The electronic component chip 5 is superior in that it can dissipate heat from the electronic component chip 5 well, and the electronic component chip 5 is made by removing the insulating layer 2, which has poor thermal conductivity, and further excavating the surface layer of the metal substrate 1. Since the electronic component chip 5 can be brought into direct contact with the metal substrate 1 and the electronic component chip 5 can be opposed to the metal substrate 1 over a wide area,
The heat of the electronic component chip 5 is effectively transferred directly to the metal substrate 1 and radiated, and the heat from the electronic component chip 5 can be efficiently radiated. Since the heat generated from the electronic component chip 5 can be effectively dissipated in this way, it is possible to increase the density of the electronic component chip 5.
ちなみにプリント配線板４の金属基板１として４２ア四
イ板（例１）を、銅−インパー−銅合金板（例２）を、
銅板（例３）をそれぞれ用いた場合についての熱伝導率
を次表に示す、比較のために、アルミナ板（比較例１）
やガラスエポキシ板（比較例２）を基板として用いたプ
リント配線板についてもその熱伝導率を示す１次表に見
られるように金属基板１である例１〜３のものは比較例
１．２のものよりも熱伝導率が高く、放熱性に優れるこ
とが確認される。また次表に示されるように比較例２の
ガラスエポキシ板を基板とするプリント配線板は吸水性
を有しており、吸湿してこの水分が電子部品チップ５に
作用するおそれがあるが、金属基板１である例１〜３の
ものでは金属基板１自体の吸水が殆どなく、しかも金属
基板１で透湿を遮断できるためにこのような電子部品チ
ップ５への水分の作用のおそれはない、さらに例１，２
のような熱膨張係数が半導体チップなど電子部品チップ
５の熱膨張係数に近いものを金属基板１として用いた場
合には、電子部品チップ５とチップキャリアとなるプリ
ント配線板４との闇の接続信頼性を向上させることがで
きることになる。特に電子部品チップ５は金属基板１と
直接接触しでいるために、この接続信頼性に対して電子
部品チップ５と金属［発明の効果］
上述のように本発明にあっては、金属基板の表面を絶縁
層で被覆すると共にこの絶縁層の表面に回路導体を設け
て金属ベースのプリント配線板を形成し、このプリント
配線板に電子部品チップを実装しであるので、チップキ
ャリアとして用いられることになるプリント配線板は金
属基板をベースとして形成されて金属基板による熱伝導
性によって放熱性が優れているものであり、しかもプリ
ント配線板の表面の一部で絶縁層及び金属基板の表層部
を切欠して四部を設け、この凹部内に電子部品チップを
実装するようにしたので、凹部内において電子部品チッ
プを金属基板に直接接触させることができると共に電子
部品チップを広い面積で金属基板と対向させることがで
きて、電子部品チップの熱を効果的に直接金属基板に伝
達させて放熱させることができ、電子部品チップからの
放熱を効率良くおこなうことができるものであって、高
密度化された電子部品チップの実装が可能になるもので
ある。またこのように放熱を得るための金属基板はプリ
ント配線板のベースを構成するものであって、放熱のた
めの特別な工夫をおこなうような必要がないものである
。By the way, the metal substrate 1 of the printed wiring board 4 is a 42A4I board (Example 1), a copper-imper-copper alloy board (Example 2),
The following table shows the thermal conductivity for each case using a copper plate (Example 3).For comparison, an alumina plate (Comparative Example 1)
As can be seen in the primary table showing the thermal conductivity of printed wiring boards using glass epoxy boards (Comparative Example 2) as substrates, Examples 1 to 3, which are metal substrates 1, have Comparative Examples 1.2. It is confirmed that the thermal conductivity is higher than that of the conventional one, and the heat dissipation property is excellent. Furthermore, as shown in the following table, the printed wiring board using the glass epoxy board of Comparative Example 2 as a substrate has water absorbing properties, and there is a risk that this water will absorb moisture and act on the electronic component chip 5; In the substrates 1 of Examples 1 to 3, the metal substrate 1 itself absorbs almost no water, and since the metal substrate 1 can block moisture permeation, there is no fear of moisture acting on the electronic component chip 5. Further examples 1 and 2
When a material whose thermal expansion coefficient is close to that of the electronic component chip 5, such as a semiconductor chip, is used as the metal substrate 1, a dark connection between the electronic component chip 5 and the printed wiring board 4 serving as a chip carrier may occur. This means that reliability can be improved. In particular, since the electronic component chip 5 is in direct contact with the metal substrate 1, the connection reliability is affected by the connection reliability between the electronic component chip 5 and the metal. The surface is covered with an insulating layer and a circuit conductor is provided on the surface of this insulating layer to form a metal-based printed wiring board, and electronic component chips are mounted on this printed wiring board, so it can be used as a chip carrier. This printed wiring board is formed based on a metal substrate and has excellent heat dissipation due to the thermal conductivity of the metal substrate.Moreover, a part of the surface of the printed wiring board is made of an insulating layer and the surface layer of the metal substrate. Since four parts are cut out and the electronic component chip is mounted in this recess, the electronic component chip can be brought into direct contact with the metal substrate within the recess, and the electronic component chip can be faced to the metal substrate over a wide area. The heat from the electronic component chip can be effectively transferred directly to the metal substrate to dissipate the heat, and the heat from the electronic component chip can be efficiently dissipated. This makes it possible to mount electronic component chips. Further, the metal substrate for obtaining heat radiation in this manner constitutes the base of the printed wiring board, and there is no need to take any special measures for heat radiation.
第１図は本発明の一実施例の断面図、第２図（ａ）（ｂ
）（ｃ）（ｄ）は同上の製造の各工程を示す断面図であ
る。
１は金属基板、２は絶縁層、３は回路導体、４はプリン
ト配線板、５は電子部品チップ、６は凹部である。Figure 1 is a sectional view of one embodiment of the present invention, Figures 2 (a) and (b)
), (c), and (d) are cross-sectional views showing each manufacturing process of the same. 1 is a metal substrate, 2 is an insulating layer, 3 is a circuit conductor, 4 is a printed wiring board, 5 is an electronic component chip, and 6 is a recessed portion.
Claims (1)
縁層の表面に回路導体を設けて金属ベースのプリント配
線板を形成し、このプリント配線板の表面の一部で絶縁
層及び金属基板の表層部を切欠して凹部を設け、この凹
部内に電子部品チップを実装して成ることを特徴とする
電子素子用チップキャリア。(1) A metal-based printed wiring board is formed by coating the surface of a metal substrate with an insulating layer and providing a circuit conductor on the surface of this insulating layer, and a part of the surface of this printed wiring board is covered with an insulating layer and a metal substrate. 1. A chip carrier for an electronic device, characterized in that the surface layer of the chip carrier is cut out to form a recess, and an electronic component chip is mounted in the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60128514A JPS61287130A (en) | 1985-06-13 | 1985-06-13 | Chip carrier for electronic element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60128514A JPS61287130A (en) | 1985-06-13 | 1985-06-13 | Chip carrier for electronic element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61287130A true JPS61287130A (en) | 1986-12-17 |
Family
ID=14986623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60128514A Pending JPS61287130A (en) | 1985-06-13 | 1985-06-13 | Chip carrier for electronic element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61287130A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020120287A1 (en) * | 2018-12-12 | 2020-06-18 | Osram Opto Semiconductors Gmbh | Substrate, assembly comprising a substrate, and method for producing a substrate |
-
1985
- 1985-06-13 JP JP60128514A patent/JPS61287130A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020120287A1 (en) * | 2018-12-12 | 2020-06-18 | Osram Opto Semiconductors Gmbh | Substrate, assembly comprising a substrate, and method for producing a substrate |
| US11923303B2 (en) | 2018-12-12 | 2024-03-05 | Osram Opto Semiconductors Gmbh | Carrier, assembly with a carrier, and method for producing a carrier |
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