JPS61286933A - Information processor - Google Patents

Abstract

PURPOSE:To prevent the titled device from malfunction due to noise or lack of a signal and to improve respose performance by fixing an allowable range of the period of a control pulse and discriminating whether the period of the control pulse is included in the allowable range or not by a discriminating circuit. CONSTITUTION:The allowable range of the input period of a control pulse is set up in a comparator 120 to discriminate whether the input period of the control pulse is included in the allowable range or not. When the period is included in the allowable range, the control of a counter device 105, the output of a manipulated variable and the processing of a CPU 101 are started by the inputted signal. When the control pulse is inputted before the passage of the lower limit value TL of the allowable range, the control pulse is regarded as noise and the start of processing to be executed under the control based upon the signal is completely inhibited. If the control pulse is not inputted after the passage of the upper limit time value TH of the allowable range is discriminated, a control pulse is generated simulatively from a discriminating circuit 113 to start the control of the counter device 105 and the processing of the CPU 101.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an information processing device that has a function to remove or compensate for noise and lack of control signals, and has a function to prevent runaway of a controlled object. [Prior Art] In recent years, the development of LSI technology has been remarkable, and along with higher integration, its functions have also become more sophisticated and multifunctional.

As performance has improved, microelectronic technology has come to be used in fields that require more complex control, such as automobiles and industrial A-bots. Coordination, high precision, and high stability are required, and countermeasures against malfunctions due to noise or signal loss become a major issue.

To control an external control object, the central processing unit (hereinafter referred to as CPU) must control the physical quantity 1, such as pulse period, voltage, and temperature, in synchronization with the i'1flJ# signal output from the control object. A common method is to take in the controlled variable, compare it with a target value, adjust the output to the controlled object (hereinafter referred to as the manipulated variable), and output the manipulated variable again in synchronization with the control signal.

However, since the control signal is mechanically generated and input to the information processing device through an external circuit, it is susceptible to external influences and is prone to noise generation and signal loss.

Therefore, if a noise with a missing symbol is detected, the CPU may calculate the manipulated variable based on the incorrect control variable, or activate the control at the wrong timing. It is possible to cause the target to go out of control.

A conventional method for preventing such malfunctions will be explained using motor speed control as an example.

The controlled variable when controlling the speed of the motor is the cycle of output pulses from a rotary encoder attached to the motor. In FIG. 3, the information processing device 300 includes a CPU 301.
Program memory 302゜Data memory 303. Internal data bus 304. It is composed of a counter 306 that counts a count clock 305 and a storage register 307 that stores the count value of the counter 306.

Next, based on this configuration, the operation of the information processing apparatus 300 will be explained using the time chart of FIG. 4.

Counter 306 counts count clock 305.

Control pulse 308, that is, encoder output pulse Pn
When T is input, the count value T of the counter 306 at that time
n is latched into the storage register 307, and immediately after that, the count value of the counter 306 is cleared to OK. Therefore, the value Tn stored in storage register 307 corresponds to the time interval between control bars AIXPn-1 and Pn.

Further, at the same time as the control pulse Pn is input, the CPU 30
9. Processing request signal 309 for 1 is active;
The CPU 301 calculates the previously calculated operation amount Yn-s = f(T
n-1), receives the control amount, that is, the content Tn of the storage register 307, via the internal bus 304, and writes the program memo! According to the procedure stored in 7302, calculation of the manipulated variable Yn = f (Tn) is executed.

Data memo! 7303 has an upper limit value TH and a lower limit value T in order to set the allowable range of the input cycle of the control pulse 308.
L 2fil type data is stored. CPU30
1 determines whether the controlled amount Tn is included in the above tolerance range (TL < T 11 < T H) before starting calculation of the manipulated variable. In FIG. 4, the control pulse P1 is input. When the CPU 301 receives the processing request signal 309, the value of the counter 306 is TI. In order to perform control with good responsiveness, the oCPU 301 immediately outputs the manipulated variable YO. Then, it is determined whether or not Ts is included in the above range, and if it is, it is assumed that the control pulse is input at a normal cycle, and the manipulated variable Yx=f(Tt) based on Ts is determined. When the zero noise P2 for performing calculation is accepted, the manipulated variable Y1 is output in synchronization with the noise to perform real-time control, but since the count value T2 is smaller than TL, it is assumed that noise has occurred. Assuming that, the manipulated variable Y based on T2
2 is not calculated, and the operation amount Y! hold. Furthermore, if the control pulse P4 is not input as a control pulse due to some disturbance, the counter 306 continues counting until the primary control pulse Ps is input. When P5 is input, the manipulated variable Yl is output, but the count value T4 is TH
It is larger and is not included in the allowable range, so it is restricted51 /<
It is assumed that the pulse 308 is missing, and the operation amount Y4 is not calculated based on T4. Thereafter, when P6 is input at a normal cycle, calculation of the manipulated variable Ys=f(Ts) is executed.

[Problem that the invention seeks to solve]

The conventional information processing apparatus described above has a major problem.

First of all, the processing request signal to the CPU is activated not only by regular control pulses but also by noise, and the CPU itself outputs the manipulated variable before determining whether it is noise or not. It is. From the viewpoint of control coordination, it is desirable to output the manipulated variable at the same time as receiving the processing request signal, but if the processing request signal is due to noise, no matter how accurate the manipulated variable is, Highly accurate control cannot be achieved if control is performed at the wrong timing.Secondly, if a control pulse is lost, it can be determined that it has been lost, but the loss cannot be compensated for and the primary Since the manipulated variable cannot be output until the control pulse is input, the control lacks coordination.

In order to compensate for the above-mentioned drawbacks, it is necessary to have a function that can remove noise and compensate for signal loss so that the correct manipulated variable can be output with correct timing. Therefore, one object of the present invention is to solve the above problems and provide an information processing device that prevents malfunctions due to noise and signal dropouts and has good responsiveness.

[Means for solving problems]

The ffN processing device based on the BAK of the present invention includes a memory unit that stores programs and various data, a central processing unit that executes processing according to the program, a counter that counts a predetermined number of clocks, and a value of the counter that is temporarily stored. a counter device comprising a storage means for storing a predetermined value; a comparison circuit for comparing the count value of the counter with the storage means for storing a predetermined value; Treatment for the device J! IJI!
Embodiment: The present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The information processing device 100 has a CPU 10I and a program memory 1.
02. Data memory 103. A counter 105 for counting the number of clocks 104 and a storage register 106 for temporarily storing the value of the counter 105. The first comparison register 107 sets the lower limit TL of the allowable range of the control pulse 1150 input cycle, and the second comparison register 1 sets the lower limit TH.
08, the counter 105 and the first comparison register 107
Alternatively, a comparator 109 that compares the values of the second comparison register 10g. and the control pulse input prohibition signal 11G, the latch pulse 111 of the storage register 106, and the CPUI Q l
Processing request signal 112 and counter clear signal 11 for
Based on this configuration, a method of noise removal and control signal interpolation will be described with reference to the time chart of FIG.

The control pulse input prohibition signal 115
Valid when 0 is inactive.

Now, when the control pulse P1 is input when the control pulse input prohibition signal 110 is in-acknowledge, the value TI of the counter 105 is latched in the storage register 106 in synchronization with it. At the same time, a processing request signal 112 to CPUl0I
and activates the control pulse input inhibition signal 110.

Immediately thereafter, the counter 105 is cleared to 0 by a counter clear signal 117 obtained by delaying the processing request signal 112 by a delay circuit 118, and starts counting again. CPU10
1 receives the processing request signal 112 and performs operation 1#Yo=f (T
O) is output to the controlled object, and storage register 1
The control #lI amount T1 stored in 06 is taken in, and calculation of the manipulated variable Ys=f(Tt) is started according to the procedure stored in the programmable memory 102. When the control pulse input prohibition signal 110 is active, the comparator 109
The -th comparison register 107 is selected as the 10,000th input. The comparator 109 compares the value of the counter 105 and the content T of the first comparison register 107, and when the two match, outputs a match signal 114 and makes the control pulse input inhibition signal inactive. That is, after one control pulse 115 is received, the first comparison register I0
The input of the control pulse 115 is prohibited until the time corresponding to the value TLK set to 7 has elapsed, and the signals P and z input during this time are considered as noise and do not generate a processing request to the CPUl0I. , counter 105
There is no need to clear the kakuto value by rattling the value of .

When the control pulse input prohibition signal 110 becomes inactive, the second comparison register 108 is selected as the input of the comparator 109. The upper limit value TH of the control pulse input period is stored in the second comparison register 108 by the CPUl0I.
is set, if the control pulse P4 is missing for some reason, the counter 105 is not cleared and T
When time H has elapsed, the match signal 114 output from the comparator 109 causes the counter to change to 2.H. Te pulse 111 is generated, and at the same time, processing request signal 1 is sent to CPUl0IK.
Activate 12. The CPU 101 receives this signal and outputs the manipulated variable Y3=f(Ta) and the manipulated variable Y4=f(
Start calculating T4).

At the same time, the control pulse input prohibition signal 110 becomes active again, and the counter clear signal 117 causes the counter 10 to
The 50 count value is OK cleared, the counting operation starts again, the first comparison register 107 is selected as the input of the comparator, and the above operation is repeated.

Therefore, in this embodiment, the upper limit value T and lower limit value TL of the allowable range (Tr, <Tn<:Ta) of the control pulse input period Tn are set in the comparator circuit, so that the control pulse input period falls within the above-mentioned allowable range. A discriminating circuit determines whether or not it is included in the range. When Tn is within the above range, the input signal activates CPU processing such as controlling the counter device, outputting the manipulated variable, and calculating a new manipulated variable. Furthermore, if a control pulse is input before the time TL has elapsed, this is regarded as noise, and all control activation using this signal is prohibited. Furthermore, it is determined that no control pulse is input even after the time 'rH has elapsed, and in this case, it is assumed that the control pulse has been lost for some reason.
Generate a pseudo K11Jlil pulse in the discrimination circuit,
This signal is used to control the pukakunta device and start processing of the CPU. In addition, once the CPU accepts a processing request, it does not need to judge whether the processing request is due to noise or whether there is a signal loss, etc., and it immediately starts calculating the manipulated variable. be able to.

〔Effect of the invention〕

As explained above, the present invention determines the permissible range of the period of the control pulse and performs the discrimination using the discrimination circuit 1.
It is possible to prohibit activation of control due to the input of more abnormal control pulses, and to activate control by compensating for the lack of necessary control pulses, unlike conventional control activation by abnormal signals. Control can be controlled in real time, eliminating the need for control to be activated due to a missing bus. Furthermore, since the correct manipulated variable based on the correct controlled variable can be output at the correct timing, the reliability of control is dramatically improved. Furthermore, unlike in the past, there is no need for the CPU to judge the occurrence of noise or signal loss, so the burden on the CPU is light and the time required to determine the manipulated variable can be shortened. As mentioned above, the information processing device based on the present invention can realize extremely reliable control.
Its practical effect is very large0

[Brief explanation of the drawing]

FIG. 1 is a detailed diagram of an information processing device having a noise removal function and a control pulse interpolation function according to the present invention, and FIG. 2 is a timing chart showing the operation of FIG. 1.
Figure 3 is a simple professional diagram showing an example of an information processing device that has conventional noise detection and pulse detection functions but does not have noise removal and interpolation functions, and Figure 4 shows the operation of Figure 3. FIG. 100.300... Information processing device, 101゜3
01...Central processing unit, 102.302・River・
・Glog2m memory, 103.303...Data memory, 104.305...Count clock, 105°306...Counter, 106.30
7...Storage register, 107...First comparison register, 108...Second comparison register, 109...Comparator, 110... ...Control pulse input prohibition signal, 111...Counter latch pulse, 112.309...Processing request signal, ixa...Discrimination circuit, 114... Coincidence signal, 115.308... Control pulse, 11
6゜304・・・Internal bus, 117・・・・・・
Counter clear signal, 118...delay circuit.

Claims (1)

[Claims] A counter device comprising a memory unit that stores programs and various data, a central processing unit that executes processing according to the program, a counter that counts a predetermined count clock, and a storage unit that temporarily stores the value of the counter. a comparison circuit for comparing the value of the counter with a storage means for storing a predetermined comparison value; and generation of a processing request signal to the central processing unit by the output of the comparison circuit and a control pulse inputted from the outside; In the information processing device, the discrimination circuit generates the processing request and controls the counter device by a control pulse inputted before a predetermined time has elapsed after the input of the control pulse. An information processing device characterized in that it does not.