JPS61286300A - Preparation of compound semiconductor single crystal having uniform characteristic - Google Patents

Abstract

PURPOSE:To make electric characteristics uniform not only in the direction of crystal face but also in the axial direction of the single crystal by cooling an ingot of a compound semiconductor single crystal after completing crystal growth in a device for the crystal growth to a specified temp. then subjecting to annealing in inert gas or in vacuum. CONSTITUTION:An ingot of a compound semiconductor single crystal is cooled after completing crystal growth temporarily to a temp. by 600-900 deg.C lower temp. than its m.p. in a crystal growth device. Then, it is heated-treated at 700-1,000 deg.C for 6-60hr in inert gas or an vacuum. By introducing, as described above, a step to cool by 600-900 deg.C lower temp. than the m.p. temporarily without cooling to room temp., the effect as described above is obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION (2) Technical Field The present invention relates to a method for improving the uniformity of axial properties of single crystal ingots of compound semiconductors such as GaAs5InP and InGaAs, and achieving this with good reproducibility between ingots.

(a) Conventional technology Compound semiconductor single crystals are manufactured using the horizontal Bridgman method (HB).
Alternatively, it is often manufactured using the liquid capsule method (LEC).

The manufactured single crystal ingot contains many crystal defects.

Defects are often evaluated based on etch pit density (EPD). Slice the ingot to make queha,
This is etched and the etch pits that appear on the surface are counted to evaluate the degree of defects contained in the single crystal. Etch pits are dislocations that appear on the Quafer cut surface, and are therefore a measure of lattice defects.

Although the LEC method and the HB method are industrially excellent methods, single crystals produced by these methods often still have many defects. For example, a diameter of 50 f made using the LEC method
For GaAs single crystals with fz or higher, the EPD is 10' c
It is in the range of In-2 to 5 x 105 cm-2.

Furthermore, the etch pits are unevenly distributed.

Even within the surface of the square, it is most common in the outer periphery, and the second largest in the center. Etch pits become fewer at positions a little further from the center. It has a W-shaped distribution. This is a problem with the in-plane etch pit distribution.

Added to this is the axial non-uniformity of the ingot.

In the case of a single crystal made by the LEC method, the EPD at the front near the seed crystal is relatively low, but the EPD increases as the distance from the seed crystal increases.

GaAs single crystal quartz field effect transistor (FE)
T) can be made. In this case, the threshold voltage Vth, which determines whether switching is turned on or off, becomes an important parameter. Although it is desirable that Vth be constant, it is normal for it to fluctuate even among quadrants.

It has been pointed out that the non-uniformity of threshold voltage Vth and the distribution of EPD have a strong correlation. For example, Miyazawa et al. Applied Physics Vol. 52 No. 3 (1988) p. 227 K
, Vth and EPD.

As with EPD, the non-uniformity of vth includes non-uniformity within the wafer plane and non-uniformity across the wafer in the axial direction of the ingot.

Although reducing dislocations is not completely equivalent to reducing variations in Vth, it is possible to improve uniformity and reduce variations in threshold voltage vth by reducing dislocations.

Annealing has been attempted to improve the uniformity of the crystal.

In some cases, the material is made into a quefer and then annealed. This is called Kuehaanir.

In some cases, the ingot is annealed. This is called ingot annealing.

(2) In group V compound semiconductor single crystals, group V elements are likely to dissociate at high temperatures, so it is necessary to take measures to prevent group V elements from escaping during annealing. For this reason, a film is sometimes attached to the quefer or ingot and annealed in this state.

Annealing may be performed in a V gas release to balance the partial pressure of the V group gas and prevent volatilization of the V group elements. Alternatively, annealing may be performed by applying high pressure with nitrogen gas or the like.

There is a report that the variation in vth within the Quafer plane is reduced by Quafer annealing. Even in ingot annealing, the direct objective is to improve uniformity on the wafer surface.

This is because a large number of integrated circuits are manufactured on a wafer, and variations in the characteristic values of the unit integrated circuits often pose a problem. Therefore, even in the case of ingot annealing, the aim was not to improve the uniformity in the axial direction of the ingot.

Therefore, in the case of ingot annealing, the pulled crystal is not annealed in its original size, but is often cut into small rounds and annealed. This is because there are restrictions on the size of the container for annealing, and because a film is attached to the surface, ingots that are smaller in size and have a uniform shape are easier to handle.

Here, we will define the term axial direction. In the case of a crystal grown by the I,EC method, the upper and lower axes are in the vertical direction, and the crystal also extends in the vertical direction. The direction in which the crystal grows is the axial direction.

When an ingot is sliced perpendicularly to the axis to form a wafer, the wafer surface is perpendicular to the axis. However, the quefer is not necessarily cut at right angles to the axis. In this case, the distribution on the wafer surface and the distribution in the axial direction are not distributions between orthogonal axes.

However, since quefers are always sliced along the axis, it is always possible to distinguish between the planar direction and the axial direction.

In the case of ingots made by the HB method, the axial direction is
The direction is along the port. Since kueha is often cut diagonally to the axis, the direction of the kueha surface and the axial direction are often not perpendicular. However, in any case, a distinction can be made.

To identify the axial location, place the one closest to the seed crystal at 70
The side opposite to the seed crystal is called the pack part. The middle part will be called the middle part.

Furthermore, since the surfaces appear only after the ingot is cut in a certain direction, the surfaces do not exist before the ingot is cut. When annealing is performed as an ingot, the plane direction refers to a plane that does not yet exist.

However, since the direction of the plane to be cut is known,
The term plane direction itself can be sufficiently defined.

Therefore, in the description of the present invention, the term surface direction is used even in the ingot state, but this does not mean that this surface already exists somewhere.

(!7) Purpose An object of the present invention is to provide a method for annealing a compound semiconductor single crystal, which produces a single crystal with uniform electrical properties not only in the plane direction but also in the axial direction. It is.

(b) The method of the present invention will be explained by taking semi-insulating undoped LEC method GaAs as an example. This is for use as a FET substrate.

A GaAs single crystal has a deep impurity level called "EL2" and a shallow impurity unit (which may be a donor level or an acceptor level).

The uniformity of the microscopic and macroscopic distribution of these two impurity units governs the electrical uniformity of the GaAs single crystal.

Macroscopically, the concentration of "EL2" units has a W-shaped distribution within the Quaha plane, and has four-fold symmetry. This corresponds well to the macroscopic density distribution of dislocations, which are a type of crystal defect. Therefore, macroscopically, the distribution of electrical properties such as specific resistance and carrier mobility also exhibits four-fold symmetry with a W-shaped distribution (or inverse W-shaped distribution).

This is what D.E. Holmes et a.
t.

“Contour maps of EL2 deep
1 level in 1quid-encapsu
rated Czochralski GaAs”
J., Appl., Phya.

55 (1984) pp. 8588.

The "EL2" concentration has variations in the axial direction and surface direction of the ingot. Furthermore, there are large variations in concentration and distribution between ingots. Variations in EL2 concentration cause non-uniformity in electrical characteristics.

On the other hand, the occurrence of dislocations depends on the thermal environment that the crystal receives during growth or cooling. In other words, the dislocation density distribution represents the thermal hysteresis experienced by the crystal.
it is conceivable that.

The origin of “EL2” is the rAs aggregate J (E
L2Family) theory has become popular. This is M
, Taniguchi et al.” 5pec
tral distribution of pho
toquenching rate and mu
ltistable 5tatesfor midg
ap electron traps (EL2f
amily ) 1nGaAs″App1. Phy
S., Lett, 45.69 (1984).

There is still no definitive theory regarding the origin of EL2, with some theories saying that it is created by oxygen atoms, and others that it is created by replacing Ga sites with As. However, the theory of "aggregation of rAs" seems to be the prevailing theory.

It has been reported that after ingot annealing, the number of "EL2" does not decrease, but the distribution becomes uniform.

D. Rum5by et al, “IMPROV
EDUNIFORMITY OF LECUNDOPE
D GALLIUM-AR5ENIDE PRODUC
ED BY HIGHTEMPERATUREANNE
AL ING″GaAs ICSymposium
(1988) IEEEp, 34-p, 37 According to this, in the temperature range of 700°C to 1000°C, 6 to
When a GaAs ingot is annealed for 60 hours, EL
2 density becomes uniform and becomes about 12 x 10''m-3.

The relationship between dislocation and EL2 is not simple.

In the case of dislocation-free crystals, the EL29 degree is uniform and low 4
It is approximately X 10” cIn-3.

GaAs with an EPD of about 10'crn-2 made by Bridgman is the same as LEC GaAs (12X 10
It has an EL2 concentration of about 15cIn-3.

In other words, the amount of dislocations and the concentration of EL2 are not proportional. However, in dislocation-free (In-doped LEC) GaAs,
The concentration of EL2 is approximately.

When these ingots are annealed in an inert gas under the above conditions, the distribution of EL2 becomes uniform.

Moreover, the concentration becomes 12X1015 cm-3. No dislocation G
For aAs crystals, this means that the EL2 concentration is increased three times by annealing.

In both LEC GaAs and HB GaAs, the EL2 concentration has a W distribution before annealing, and has 4-fold symmetry.

In In-doped dislocation-free GaAs, the EL2 concentration is low and uniform.

When these ingots are annealed, the EL2 concentration is
All ingots are made uniform.

The W distribution disappears, the 4-fold symmetry is no longer observed, and the EL2 concentration becomes approximately the same value 12×10′σ−3 for any ingot.

However, dislocations are unchanged by annealing.

Dislocations do not disappear, decrease, or increase.

The value of the threshold voltage vth that determines the electrical characteristics of the FET is E
I already mentioned that it depends on the distribution of L2. Although this is not solely due to the distribution of EL2, it seems that this has a strong correlation.

The magnitude of the concentration of EL2 is not very important, but the fluctuation of the concentration is the problem.

The dislocation density of an ingot changes both in the planar and axial directions. Similarly, the EL2 distribution also fluctuates in the planar and axial directions.

If the ingot contains a dislocation-free part, the EL
The average value of the two concentrations also fluctuates in the axial direction. Since the EL2 concentration has a strong relationship with the threshold voltage when fabricated into an FET, when an FET is made on a wafer cut from such an ingot, the threshold voltage is There will be variations between them. The entire distribution of the threshold voltage within the quadrature plane differs vertically between the quadrature taken from the front portion of the ingot and the quadrature taken from the pack portion.

However, as mentioned above, it has been reported that when a GaAs ingot is annealed, the distribution of the EL2 concentration becomes flat, and the average straightness of the EL2 concentration remains almost constant regardless of the height or fall of the EPD before annealing. has been done.

This is strange.

Annealing does not reduce EPD. Furthermore, the etch bit has four-fold symmetry. This symmetry is not lost by annealing.

Before annealing, the EL2 concentration has a W-shaped distribution similar to that of the etch pits, and has 4-fold symmetry. However, due to ingot annealing, only the EL2 concentration loses its W-shaped distribution and also loses its 4-fold symmetry.

This experiment is not necessarily reliable because the amount of data is small. However, it seems to be clear that there is no direct relationship between EL2 concentration and EPD concentration. As mentioned above, measurement of EL2 concentration has been carried out by many researchers, and there are various theories regarding its origin.

The theory of "aggregation of rAs" seems to be the most likely, but this is also not conclusive.

Therefore, the present inventor temporarily cooled the single crystal after crystal growth to a temperature 600°C to 900°C lower than the melting point without cooling it to room temperature, and then heated it in an inert gas or vacuum. We came up with a method of heat treatment at a temperature range of 700°C to 1000°C for 6 hours to 60 hours.

The second half of the annealing is well known, and the atmosphere,
Both temperature and time have already been tried.

The first stage of processing is new.

This is to form "EL2" which is a deep impurity unit throughout the crystal ingot.

Regardless of the LEC method or the HB method, after the single crystal is grown, it is gradually cooled down to room temperature and taken out of the furnace. In other words, once it reaches room temperature.

If you don't do this, you won't be able to perform the necessary processing.

Even though it is called ingot annealing, it does not mean that the entire ingot is annealed. Since the container is very restrictive, it is cut into several pieces, placed in a capsule, and heated in a vacuum or in a nitrogen or argon gas atmosphere.

However, if you do this, you will have to bring it down to room temperature.

The inventor thought that at this time, the EL2 distribution would occur non-uniformly in the ingot axial direction.

The temperature distribution during the cooling process in the furnace is not uniform in the axial direction. Due to the location of the heaters, the first part of the ingot to solidify is at a low temperature, and the last part to solidify is at a high temperature.

Since the temperature decreases in such a non-uniform temperature, the amount of generated EL2 units is radiated in the axial direction and varies greatly.

In the present invention, cooling is stopped midway through without lowering to room temperature,
By annealing in the same furnace, the aim is to make the generation of the EL2 level more uniform from the beginning. Since the annealing is performed in the same furnace, this furnace doubles as a crystal growth furnace and an annealing device.

The temperature is lowered below the melting point in the range of 600°C to 900°C in order to generate EL2 units.

The purpose of annealing next is to redistribute the EL2 levels thus created and make them uniform.

The temperature range is from 600℃ to 900℃ from the melting point.
a For an As single crystal, this means 738°C to 438°C. If the temperature is lowered to 900° C. or lower, EL2 will be generated unevenly, which is not desirable. By non-uniform, I mean in the axial direction rather than in the planar direction, which is different from the conventional method, which is once cooled to room temperature.

EL2 units cannot be formed in the crystal unless the temperature is lowered to below 600"C below the melting point.If the EL2 level is not in the crystal,
This cannot be redistributed by annealing.

Regarding the annealing temperature, when the annealing temperature is set to 1000° C. or higher, group V elements are violently dissociated from the crystal surface, which deteriorates the characteristics of the crystal. Also, if the temperature is 700℃ or less, EL
No redistribution of the two levels occurs.

(B) Example low chromium doped semi-insulating G grown by LEC method
The method of the invention was applied to aAs crystals.

For comparison, a GaAs crystal to which the method of the present invention was not applied was also produced. The axial electrical characteristics of one ingot,
In addition to this, it is necessary to investigate differences in electrical properties between ingots. For this reason, seven ingots were made and their properties were compared.

Since we are comparing the variation in the threshold voltage vth, we turn the ingot into a wafer, make nWUfA there, attach electrodes, measure the C-V characteristics, and calculate the pinch-off voltage Vp.
I asked for

The GaAs single crystal to which the method of the present invention was applied was first cooled to 450°C to 550°C. This is LE
This is done in the C device. The temperature of the crystal during cooling differs considerably between the top and bottom, but the difference in temperature between the top and bottom can be reduced by providing an insulating tube surrounding the cooling zone or by using an after-heating heater.

Th 7 ingots 1. ~Suppression 7. shall be.

(1) NIIL 1 and 11h2 were annealed at 700℃ for 6 hours (2) Fkx 8 and 11h2 were annealed at 700℃ for 1
2 hours annealing (3) 1 rainbow 5 and l! lL6 is 800
Annealing at 800°C for 6 hours (4) lh7 was annealed at 800°C for 12 hours. Since this is carried out using an LEC device, another annealing heater is provided at the position where the crystal is pulled up and cooled, or above it, and the crystal is heated by this.

This can also be used as the above-mentioned after-heater. in this case,
The crystal is long vertically, but so that the temperature at the top and bottom is the same,
Set the length, position, or height of the heater.

The pinch-off voltage vp is measured for the 7-wood ingot that has been heat-treated in this way and the other 7-wood ingots that have not been heat-treated. The procedure for measuring this is well known and all procedures are the same.

Take out the ingot from the LEC device. Take out one sample from the front section and one sample from the pack section. All ingots have a diameter of 55 m (55±3 h) and a length of approximately 50 m. The front sample was cut out at a position 10wIt from the top of the crystal. A sample of the pack part was cut out at 40 mm from the top edge (10 mm from the bottom edge).

The sliced kuehaya is subjected to normal processing to become a mirror kuehaya. That is, it is made into a mirror surface through the processes of beveling, etching, wrapping, etching, and polishing.

This quefer is semi-insulating, but Si ions can be heated at 180K.
Ions were implanted at a density of 8 x 1012 cm-2 at an acceleration of eV to form an n-type layer.

Furthermore, the SiO□ film was deposited with a
0°C was deposited, and annealing was performed at 820°C for Cl2O in a nitrogen atmosphere. This is to activate the implanted impurities and restore the lattice structure. This is always performed after ion implantation, and unlike ingot annealing, it does not reduce variations in electrical characteristics and takes a short time.

After this, the 5i02 film is removed. Deposited gold, diameter 200
A large number of Schottky electrodes of μmφ were formed on the active layer.

Using this electrode, C-■ measurement was performed. A C-7 curve as shown in FIG. 2 is obtained. The voltage Vp at which the slope of C with respect to V becomes large is defined as the pinch-off voltage V.

Such data was obtained for many points on the wafer. The average value of this voltage is the pinch-off voltage V of this wafer.
Let it be p.

Wafers of the front part (S) and the bank part (1) are cut out from seven ingots. The average value of this pinch-off voltage on the wafer is shown in FIG. 1(a).

The horizontal axis is Kueha-Ki. S corresponds to the wafer taken from the front, and T corresponds to the wafer taken from the bank. The vertical axis is the pinch-off voltage V
It is p. FIG. 1(a) shows the average value of the pinch-off voltage for wafers taken from ingots that have undergone the cooling and annealing process according to the present invention as white circles. In order to easily show the correspondence, the annealing temperature and annealing time are written directly below it. Pinch-off voltage is -41 to -5,4
It is between v.

For comparison, seven ingots No. 8 to No. 14 to which the method of the present invention was not applied were similarly made into mirror wafers, doped with Si to form active layers, and the pinch-off voltages were measured.

The results are shown in FIG. 1(b). S is for front;
T is the wafer cut out from the puncture. Similarly, the pinch-off voltage Vp is measured at a large number of measurement points on the wafer, and the average value is calculated. This is shown by a black circle, and the pinch-off voltage is between -3.8V and -6.48V.

It can be seen that the pinch-off voltage V9 of the n-layer made from the ingot improved by the method of the present invention has less variation.

Ml 1. , lk 5. , +4a 6. From etc., vp
It becomes clear that the difference between the front and back of the image is decreasing.

What is surprising is that the difference in Vp between ingots becomes smaller.

There is a difference in pinch-off voltage of about 2.6 V between the magnet 9 and the magnet 11 to which the method of the present invention was not applied. On the other hand, among those to which the present invention is applied, the largest difference is between Kame 2 and Kame 7, but it is still only 1.3V.

Φ) Effects (1) A single crystal with uniform electrical properties can be created in the axial direction of the ingot.

(2) Electrical characteristics can be made substantially uniform between different ingots. Since the electrical characteristics are stable from ingot to ingot, it is possible to make FET substrate materials with good reproducibility.

[Brief explanation of drawings]

FIG. 1(a) shows a Cr-doped film made by the method of the present invention. Front part (S) and pack part (1) of GaAs ingot
) The average value of the pinch-off voltage at ) is marked with a white circle. There are 7 ingots, N11. ~Number 7. numbered. The annealing conditions are listed below. Figure 1(b) shows seven Cr-doped GaA films made using the conventional method.
It is a diagram showing the average value of the pinch-off voltage in the front part (S) and the pack part (1) of the S ingot with black circles. The ingots were numbered 8 to 14. FIG. 2 is a graph illustrating a method for determining the pinch-off voltage Vp from the C-7 curve. Inventor Masamichi Yokoyo Nishine Shibe Matsumoto Aikachi Hiroshi Morishita 1) Keiichi Part Patent Applicant Sumitomo Electric Industries, Ltd. No. 1 (a) (v) According to the present invention (b) 4 Kita 1

Claims (1)

[Claims] After crystal growth, the compound semiconductor single crystal ingot is cooled in a crystal growth apparatus to a temperature 600 to 900 degrees Celsius lower than its melting point, and then cooled to a temperature of 700 to 1000 degrees Celsius in an inert gas atmosphere or in vacuum. 6 hours or more in the range 6
1. A method for producing a compound semiconductor single crystal having uniform characteristics, the method comprising heat-treating for 0 hours or less.