JPH09199380A - Si substrate for epitaxial wafer and its manufacturing method - Google Patents

Si substrate for epitaxial wafer and its manufacturing method

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Publication number
JPH09199380A
JPH09199380A JP2216196A JP2216196A JPH09199380A JP H09199380 A JPH09199380 A JP H09199380A JP 2216196 A JP2216196 A JP 2216196A JP 2216196 A JP2216196 A JP 2216196A JP H09199380 A JPH09199380 A JP H09199380A
Authority
JP
Japan
Prior art keywords
silicon substrate
boron concentration
heat treatment
epitaxial
boron
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2216196A
Other languages
Japanese (ja)
Inventor
Hiroshi Shirai
宏 白井
Ryuji Takeda
隆二 竹田
Rii Tsuon
ツォン・リー
Tateo Hayashi
健郎 林
Atsushi Yoshikawa
淳 吉川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Coorstek KK
Original Assignee
Toshiba Ceramics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Ceramics Co Ltd filed Critical Toshiba Ceramics Co Ltd
Priority to JP2216196A priority Critical patent/JPH09199380A/en
Publication of JPH09199380A publication Critical patent/JPH09199380A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To produce an epitaxial wafer to be used for semiconductor devices required to realize a more high degree of integration; the wafer having a superior crystallinity without involving any dislocation in surface Si single crystal and no defect in view of the fine structure. SOLUTION: A Si substrate is heavily doped with B to provide a specified B concn. [B0 ]. Its surface B concn. Bs at its outermost face to grow an epitaxial film is 1.5×10<16> atoms/cm<3> or less and the B concn. increases at a gradient up to a B concn. [Bx ] higher than [B0 ]×0.5 in the depth of at least 2 microns from the outermost face. The substrate having the B concn. [B0 ] resulting from a heavy doping of B for epitaxial wafers can be produced by heat treating its surface to grow the epitaxial film in a H-containing gas atmosphere with [Bs ] of at least 1.5×10<16> atoms/cm<3> or less.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、エピタキシャルウ
エハ用シリコン基板及びその製造方法に関し、詳しく
は、表面にシリコン単結晶を反りや結晶格子歪み無く結
晶性よくエピタキシャル成長可能なボロンドープシリコ
ン基板で、最終的に高性能な超LSI等半導体デバイス
の製造を可能とするエピタキシャルウエハ用シリコン基
板及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon substrate for an epitaxial wafer and a method for manufacturing the same, and more specifically, it is a boron-doped silicon substrate capable of epitaxially growing a silicon single crystal on the surface without warping or crystal lattice distortion with good crystallinity. TECHNICAL FIELD The present invention relates to a silicon substrate for an epitaxial wafer and a method for manufacturing the same, which makes it possible to manufacture semiconductor devices such as ultra-high performance ultra-LSI.

【0002】[0002]

【従来の技術】近年の半導体デバイスの高集積化は著し
いものがあり、その基板であるシリコンウエハにおいて
も高性能が要求されより結晶性のよいものが望まれてい
る。このため、従来からDRAMやMPU用基板のウエ
ハとしてはエピタキシャルシリコンウエハが使用されて
いる。エピタキシャルシリコンウエハは、一般に、キャ
リア源、例えばボロン(B)が8.49×1018〜2.
01×1019atoms/cm3 の高濃度にヘビードー
プされた約5〜10mΩcmの低比抵抗のシリコン基板
表面上に、数μmの厚さでシリコン単結晶膜をエピタキ
シャル成長させたものである。このエピタキシャルシリ
コンウエハの表面に形成されるエピタキシャルシリコン
単結晶膜は、例えば、比抵抗約5〜10Ωcmのボロン
濃度1.34×1015〜2.70×1015atoms/
cm3 のライトドープ状態にある。このようなエピタキ
シャルシリコンウエハのエピタキシャル成長させた高結
晶性のシリコン膜上にデバイスを形成し高性能を確保し
ているのが現状である。
2. Description of the Related Art In recent years, the degree of integration of semiconductor devices has been remarkably high, and a silicon wafer, which is a substrate thereof, is required to have high performance and to have better crystallinity. Therefore, an epitaxial silicon wafer has been conventionally used as a wafer for a DRAM or MPU substrate. Epitaxial silicon wafers generally have a carrier source, for example, boron (B) of 8.49 × 10 18 to 2.
A silicon single crystal film was epitaxially grown to a thickness of several μm on a surface of a silicon substrate having a low specific resistance of about 5 to 10 mΩcm, which was heavily doped at a high concentration of 01 × 10 19 atoms / cm 3 . The epitaxial silicon single crystal film formed on the surface of this epitaxial silicon wafer has, for example, a boron concentration of 1.34 × 10 15 to 2.70 × 10 15 atoms / at a specific resistance of about 5 to 10 Ωcm.
It is in a lightly doped state of cm 3 . At present, high performance is ensured by forming devices on a highly crystalline silicon film epitaxially grown on such an epitaxial silicon wafer.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、昨今の
超LSIに代表される超高集積度の半導体メモリーで
は、エピタキシャルウエハ表面にサブミクロンオーダー
の素子を形成することが通常であり、表面のシリコン単
結晶が良好な結晶性を有していても、ウエハ全体の微細
構造における歪みや微量組成分の差異が存在する場合
は、それら微小な構造的歪みが最終的な半導体デバイス
に多大な影響を及ぼすことになる。一方、デバイスが形
成されるシリコンエピタキシャル膜は、上記したように
所定のボロン濃度のシリコン基板上にボロン濃度を異に
してエピタキシャル成長され、基板との界面では拡散に
よるオートドープ現象があるとはいえボロン濃度がステ
ップ関数的に階段状に急激に変化することになる。発明
者らは、エピタキシャルウエハ内の上記のような構成組
成の急激な変化はエピタキシャルウエハ全体に影響を与
えると共にエピタキシャル膜にも何らかの不都合を生じ
させるものと確信し、エピタキシャルウエハを構成する
シリコン基板とその表面のエピタキシャル膜について微
細構造的な検討を進めた。その結果、シリコン基板とエ
ピタキシャルシリコン膜との界面でのボロン濃度の変化
が、エピタキシャルウエハにおける格子構造的歪みや構
造的反りを起こし、また、シリコン格子定数の不連続変
化にも相応してその緩和応力によるエピタキシャル結晶
での転位のおそれをもたらすことを知見し、より一層の
高集積化が求められる半導体デバイスの基板としてより
完全で高結晶のエピタキシャルウエハを提供すべく本発
明に到った。
However, in ultra-high integration semiconductor memories represented by VLSIs of recent years, it is usual to form sub-micron-order elements on the surface of an epitaxial wafer, and only silicon on the surface is formed. Even if the crystal has good crystallinity, if there are strains in the microstructure of the entire wafer and differences in trace amounts, these microstructural strains have a great impact on the final semiconductor device. It will be. On the other hand, a silicon epitaxial film on which a device is formed is epitaxially grown on a silicon substrate having a predetermined boron concentration with different boron concentrations as described above, and although there is an auto-doping phenomenon due to diffusion at the interface with the substrate, boron is formed. The concentration suddenly changes stepwise in a step function. The inventors are convinced that the abrupt change in the compositional composition in the epitaxial wafer as described above affects the entire epitaxial wafer and causes some inconvenience to the epitaxial film. We proceeded with a microstructural study of the epitaxial film on the surface. As a result, the change in the boron concentration at the interface between the silicon substrate and the epitaxial silicon film causes lattice structural distortion and structural warp in the epitaxial wafer, and the relaxation is also corresponding to the discontinuous change in the silicon lattice constant. The present inventors have found that there is a risk of dislocation in an epitaxial crystal due to stress, and have arrived at the present invention to provide a more complete and highly crystalline epitaxial wafer as a substrate of a semiconductor device for which higher integration is required.

【0004】[0004]

【課題を解決するための手段】本発明によれば、所定に
ヘビードープされたボロン濃度[B0 ]を有するシリコ
ン基板であって、該基板のエピタキタシャル膜を成長さ
せる最表面における表面ボロン濃度[BS ]が1.5×
1016atoms/cm3 以下であり、且つ、[B0
×0.5以上のボロン濃度[BX ]まで該最表面から少
なくとも2μmの深さに亘りボロン濃度が勾配を有して
逓増することを特徴とするエピタキシャルウエハ用シリ
コン基板が提供される。本発明のエピタキシャルウエハ
用シリコン基板において、前記ボロン濃度[B0 ]が1
×1017atoms/cm3 以上であることが好まし
い。
According to the present invention, a silicon substrate having a predetermined heavy-doped boron concentration [B 0 ] and a surface boron concentration at the outermost surface of the substrate on which an epitaxial film is grown. [B S ] is 1.5 ×
10 16 atoms / cm 3 or less, and [B 0 ]
There is provided a silicon substrate for an epitaxial wafer, wherein the boron concentration has a gradient and gradually increases from the outermost surface to a depth of at least 2 μm up to a boron concentration [B X ] of 0.5 or more. In the silicon substrate for an epitaxial wafer of the present invention, the boron concentration [B 0 ] is 1
It is preferably × 10 17 atoms / cm 3 or more.

【0005】また、本発明は、所定にヘビードープされ
たボロン濃度[B0 ]を有するシリコン基板のエピタキ
タシャル膜を成長させる表面を、水素含有ガス雰囲気下
で熱処理して、少なくとも最表面ボロン濃度[BS ]を
1.5×1016atoms/cm3 以下とすることを特
徴とするエピタキシャルウエハ用シリコン基板の製造方
法を提供する。本発明のエピタキシャルウエハ用シリコ
ン基板の製造方法において、前記水素含有ガスが、水素
ガスとアルゴンガスが容量比H2 /Ar>1の混合ガス
であることが好ましい。
Further, according to the present invention, the surface of the silicon substrate having a predetermined heavy-doped boron concentration [B 0 ] on which the epitaxial film is to be grown is heat-treated in a hydrogen-containing gas atmosphere to obtain at least the outermost boron concentration. Provided is a method for manufacturing a silicon substrate for an epitaxial wafer, characterized in that [B S ] is set to 1.5 × 10 16 atoms / cm 3 or less. In the method for producing a silicon substrate for an epitaxial wafer according to the present invention, it is preferable that the hydrogen-containing gas is a mixed gas of hydrogen gas and argon gas having a volume ratio H 2 / Ar> 1.

【0006】上記本発明のエピタキシャルウエハ用シリ
コン基板の製造方法の熱処理は、実質的に水素含有ガス
雰囲気において1000〜1200℃の温度で30〜4
60分間処理して行われることが好ましく、例えば、処
理時間が、次式:DT △tT =∫I FD(T)dt(但し、∫I FD
(T)dtは、熱処理工程における熱処理開始から熱処理終
了まで(実質的に1000℃以上での昇温から冷却工程
を含む)のボロンの拡散を示し、DT はT℃におけるボ
ロンの拡散係数(cm2 /秒)であり、△tT はT℃相
当熱処理時間、即ち、熱処理全工程をT℃で熱処理する
と仮定したときに要する熱処理時間(秒)である。)で
表わされる△tT であることが好ましい。
The heat treatment in the method for producing a silicon substrate for an epitaxial wafer according to the present invention is carried out in a hydrogen-containing gas atmosphere at a temperature of 1000-1200 ° C. for 30-4.
Is preferably carried out for 60 minutes, for example, processing time, the following equation: D T △ t T = ∫ I F D (T) dt ( where, ∫ I F D
(T) dt represents the diffusion of boron from the start of the heat treatment in the heat treatment step to the end of the heat treatment (including the temperature increase from substantially 1000 ° C. to the cooling step), and D T represents the diffusion coefficient of boron at T ° C. ( cm 2 / sec) and Δt T is the heat treatment time corresponding to T ° C., that is, the heat treatment time (sec) required assuming that all the heat treatment steps are performed at T ° C. ) It is preferable that it is Δt T.

【0007】本発明のエピタキシャルウェハ用シリコン
基板は上記のように構成され、シリコン基板のエピタキ
シャル膜が形成される表面のキャリア源のボロン濃度を
所定の1.5×1016atoms/cm3 以下とするた
め、1×1015〜1×1016atoms/cm3 のライ
トドープ状態のエピタキシャル膜との界面でのボロン濃
度ギャップが著しく低減させられることから、結晶格子
歪みを減少できると共にエピタキシャル膜の結晶転位も
抑制でき、より完全性のよいシリコン結晶を得ることが
できる。また、所定深さのシリコン基板内部から表面へ
ボロン濃度を勾配を有して逓減させ表面で上記の所定濃
度となすことから、格子定数の不連続性を解消でき、格
子歪みを低減してエピタキシャル膜の特性の低下を防止
でき、ひいては信頼性高い良好な素子特性を有するデバ
イスを歩留りよく提供することができる。また、上記の
ようなエピタキシャルウェハ用シリコン基板は、シリコ
ンウエハを水素含有雰囲気下で所定条件で熱処理するこ
とにより容易に製造することができ、工業的実用性が極
めて高い。
The silicon substrate for an epitaxial wafer of the present invention is configured as described above, and the boron concentration of the carrier source on the surface of the silicon substrate on which the epitaxial film is formed is set to a predetermined value of 1.5 × 10 16 atoms / cm 3 or less. Therefore, the boron concentration gap at the interface with the epitaxial film in the lightly doped state of 1 × 10 15 to 1 × 10 16 atoms / cm 3 can be significantly reduced, so that the crystal lattice strain can be reduced and the crystal of the epitaxial film can be reduced. Dislocations can also be suppressed, and a silicon crystal with better integrity can be obtained. Further, since the boron concentration is gradually decreased from the inside of the silicon substrate of a predetermined depth to the surface with a gradient to obtain the above predetermined concentration on the surface, the discontinuity of the lattice constant can be eliminated and the lattice strain can be reduced to reduce the epitaxial strain. It is possible to prevent the deterioration of the film characteristics, and to provide a highly reliable device having good element characteristics with high yield. Further, the silicon substrate for an epitaxial wafer as described above can be easily manufactured by heat-treating the silicon wafer in a hydrogen-containing atmosphere under predetermined conditions, and has extremely high industrial practicality.

【0008】[0008]

【発明の実施の形態】以下、本発明について詳細に説明
する。本発明のシリコン基板は、従来公知のp型半導体
用のボロンを1017atoms/cm3 以上の濃度にヘ
ビードープしたものを用いることができ、その表面は通
常のウエハと同様に所定の結晶面にスライスされ、鏡面
状に研磨されたものが用いられる。次に、上記のボロン
をヘビードープしたシリコンウエハ上にシリコン膜をエ
ピタキシャル形成した場合に、結晶格子歪み等の微細構
造での不都合が生じることについて説明する。ボロンに
よりドープされたシリコンの格子定数は、例えば「ラ・
メタルルジア・イタリアナ(la metallurgia itallian
a) 」第65巻第23頁(1973年)によれば、シリ
コンの格子定数5.4305Åに対しボロン濃度[B]
≧1×1019atoms/cm3 で5.43038Å以
下となることが報告されており、[B]<1×1019
toms/cm3 の場合には(5.4305−5.43
038)=1.2×10-4Å以下となり変化が僅少であ
ることが知られる。従って、エピタキシャルウエハにお
ける通常の1×1016atoms/cm3 以下のボロン
ライトドープであればシリコン結晶格子定数の変化が小
さく、結晶格子の歪みもそれほど問題にする必要がない
ものと推定される。発明者らはこの点を鑑み、ボロン濃
度[B]=1.3×1019atoms/cm3 程度のヘ
ビードープシリコン基板とボロン濃度[B]=2×10
15atoms/cm3 程度のライトドープシリコン基板
とをそれぞれラマンスペクトル分析により結晶性につい
て確認した。その結果、図1にライトドープシリコン基
板及び図2にヘビードープシリコン基板のラマンスペク
トルを示したように、ライトドープシリコン基板に比し
ヘビードープシリコン基板は、スペクトルが低波数側に
シフトし結晶格子に歪みが生じていること、半値幅が増
大し結晶性が低下していることが明らかである。また、
これらからヘビードープシリコン基板上にライトドープ
のシリコンエピタキシャル膜を形成すれば、界面での格
子歪みが生じることも確認された。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below. As the silicon substrate of the present invention, a conventionally well-known heavily-doped boron for p-type semiconductor at a concentration of 10 17 atoms / cm 3 or more can be used, and its surface has a predetermined crystal plane like a normal wafer. Sliced and mirror-polished is used. Next, it will be described that when a silicon film is epitaxially formed on a silicon wafer heavily doped with boron as described above, inconvenience occurs in a fine structure such as crystal lattice distortion. The lattice constant of silicon doped with boron is, for example,
La metallurgia itallian
a) ”, Vol. 65, page 23 (1973), according to the lattice constant of silicon, 5.4305 Å, the boron concentration [B].
It has been reported that at ≧ 1 × 10 19 atoms / cm 3 , it is less than or equal to 5.43038 Å, and [B] <1 × 10 19 a
In the case of toms / cm 3 , (5.4305-5.43)
038) = 1.2 × 10 −4 Å or less, and it is known that the change is slight. Therefore, it is presumed that the boron crystallite doping of 1 × 10 16 atoms / cm 3 or less, which is a usual value in an epitaxial wafer, causes a small change in the silicon crystal lattice constant, and the distortion of the crystal lattice does not have to be a problem. In view of this point, the inventors have considered a heavy-doped silicon substrate having a boron concentration [B] = 1.3 × 10 19 atoms / cm 3 and a boron concentration [B] = 2 × 10.
The crystallinity of the light-doped silicon substrate of about 15 atoms / cm 3 was confirmed by Raman spectrum analysis. As a result, as shown in the Raman spectra of the light-doped silicon substrate in FIG. 1 and the heavy-doped silicon substrate in FIG. 2, as compared with the light-doped silicon substrate, the heavy-doped silicon substrate has a spectrum shifted to a lower wavenumber side and a crystal lattice. It is clear that the strain is generated, the full width at half maximum is increased, and the crystallinity is decreased. Also,
From these, it was also confirmed that when a light-doped silicon epitaxial film was formed on a heavy-doped silicon substrate, lattice strain occurred at the interface.

【0009】本発明において、エピタキシャル膜を形成
するシリコン基板の表面ボロン濃度[BS ]を、上記の
ヘビードープシリコン基板のボロン濃度[B0 ]>10
17atoms/cm3 から1.5×1016atoms/
cm3 以下に低減する。上記の報告では、1×1019
toms/cm3 よりボロン濃度が低い場合にはシリコ
ンの結晶格子定数の変化は僅少であり格子歪みは少な
い。しかし、エピタキシャルウエハのシリコン基板上に
形成されたエピタキシャル膜のボロン濃度は1×1015
〜1016atoms/cm3 であり、前記したようにシ
リコン基板との界面でのボロン濃度の急変はエピタキシ
ャル膜の結晶転位を生起させるおそれがあり、同様のボ
ロン濃度[BS ]1.5×1016atoms/cm3
表面とすることが好ましい。表面ボロン濃度[BS ]が
1.5×1016atoms/cm3を超えた場合は、シ
リコン基板との界面で格子歪が大きくなり好ましくな
い。
In the present invention, the surface boron concentration [B S ] of the silicon substrate forming the epitaxial film is set to the boron concentration [B 0 ]> 10 of the above heavy-doped silicon substrate.
17 atoms / cm 3 to 1.5 × 10 16 atoms /
Reduce to cm 3 or less. In the above report, 1 × 10 19 a
When the boron concentration is lower than toms / cm 3, the change in the crystal lattice constant of silicon is small and the lattice strain is small. However, the boron concentration of the epitaxial film formed on the silicon substrate of the epitaxial wafer is 1 × 10 15
-10 16 atoms / cm 3 , and as described above, a sudden change in the boron concentration at the interface with the silicon substrate may cause crystal dislocation in the epitaxial film, and the same boron concentration [B S ] 1.5 × A surface of 10 16 atoms / cm 3 is preferable. If the surface boron concentration [B S ] exceeds 1.5 × 10 16 atoms / cm 3 , the lattice strain becomes large at the interface with the silicon substrate, which is not preferable.

【0010】本発明のエピタキシャルウエハ用シリコン
基板は、上記の表面ボロン濃度を有すると共に、シリコ
ン基板の内部方向へ少なくとも約2μmの深さでボロン
濃度が濃度勾配を有して逓増し、シリコン基板のヘビー
ドープボロン濃度[B0 ](>1017atoms/cm
3 の50%以上のボロン濃度、即ち[B0 ]×0.5以
上のボロン濃度[BX ]に至り、最終的に最内部は元々
のヘビードープボロンのシリコン基板で構成される。内
部方向に少なくとも約2μmの深さでボロン濃度に勾配
を持たせるのは、シリコン基板とエピタキシャル膜との
界面での格子歪みを小さくするためである。ボロン濃度
が勾配を有して逓増する深さが2μm未満であると界面
でのボロン濃度プロファイルの立ち上がりが急になり、
ステップ関数に近い状況となり、界面での格子歪みが無
視し得なくなり好ましくない。また、2μmの深さのボ
ロン濃度[BX ]がヘビードープボロン濃度[B0 ]の
50%以上であるとしたのは、ボロン濃度の深さ方向の
プロファイルをバルク部のボロン濃度に漸近的に近づけ
るためである。
The silicon substrate for an epitaxial wafer of the present invention has the above surface boron concentration, and the boron concentration gradually increases toward the inside of the silicon substrate at a depth of at least about 2 μm with a concentration gradient. Heavy-doped boron concentration [B 0 ] (> 10 17 atoms / cm 3)
A boron concentration of 50% or more of 3 , that is, a boron concentration [B x ] of [B 0 ] × 0.5 or more is reached, and finally the innermost portion is composed of the original heavy-doped boron silicon substrate. The reason that the boron concentration has a gradient in the inner direction at a depth of at least about 2 μm is to reduce the lattice strain at the interface between the silicon substrate and the epitaxial film. If the boron concentration has a gradient and the depth of increase is less than 2 μm, the boron concentration profile at the interface rises rapidly,
The situation is close to a step function, and the lattice strain at the interface cannot be ignored, which is not preferable. The reason that the boron concentration [B X ] at a depth of 2 μm is 50% or more of the heavy doped boron concentration [B 0 ] is that the profile of the boron concentration in the depth direction is asymptotic to the boron concentration in the bulk portion. To get closer to.

【0011】前記のように本発明のエピタキシャルウエ
ハ用シリコン基板は、表面がエピタキシャル膜の有する
所定のボロン濃度を有し、且つ、その内部方向に所定深
さでシリコン基板が有するボロン濃度の所定比率の濃度
まで逓増し内部的には本来のシリコン基板を保持するこ
とから、表面に形成されるボロンライトドープのエピタ
キシャル膜の格子定数変化が小さい良好な結晶性を損な
うことがない。そのため、最終的に良好なデバイス形成
領域を確保でき、デバイス製造工程中での結晶転位の発
生を抑制することができ、製造されるデバイスの特性、
信頼性を向上させることができる。
As described above, the silicon substrate for an epitaxial wafer according to the present invention has a predetermined boron concentration on the surface thereof, and a predetermined ratio of the boron concentration of the silicon substrate at a predetermined depth inward thereof. Since the silicon substrate is gradually increased to the above concentration and the original silicon substrate is retained internally, the crystallinity of the boron light-doped epitaxial film formed on the surface is small and the good crystallinity is not impaired. Therefore, it is possible to finally secure a good device formation region, it is possible to suppress the occurrence of crystal dislocation during the device manufacturing process, the characteristics of the device to be manufactured,
Reliability can be improved.

【0012】本発明のエピタキシャルウエハ用シリコン
基板の製造方法は、上記した各要件を具備させることが
できればよく、特に制限されるものでない。例えば、以
下の方法で製造することができる。即ち、先ず、通常の
チョクラルスキー法等で引き上げられ、公知の方法によ
りスライス、研磨等の諸工程を経て鏡面研磨され、ボロ
ン濃度が1×1017atoms/cm3 以上のシリコン
ウェハを製造する。次いで、製造されたシリコンウェハ
を、水素含有ガス雰囲気下で熱処理することにより所定
要件を具備するように構成することができる。本発明の
水素含有ガス雰囲気下での熱処理は、所定のボロンドー
プのシリコンウェハを、実質的に水素ガスまたはAr、
窒素等の不活性ガスと水素ガス50容量%以上の混合ガ
ス等の水素含有ガス雰囲気中で、1000〜1200℃
の温度で30〜460分間処理することで行われ、ボロ
ンヘビードープのシリコン基板の表面のボロンを外方拡
散させて、少なくともエピタキシャル成長させる最表面
のボロン濃度を1.5×1016atoms/cm3 以下
とする。
The method for producing a silicon substrate for an epitaxial wafer according to the present invention is not particularly limited as long as it can satisfy the above requirements. For example, it can be manufactured by the following method. That is, first, a silicon wafer having a boron concentration of 1 × 10 17 atoms / cm 3 or more is manufactured by pulling it up by an ordinary Czochralski method or the like, and performing mirror polishing through various steps such as slicing and polishing by a known method. . Next, the manufactured silicon wafer can be heat-treated in a hydrogen-containing gas atmosphere so as to meet the predetermined requirements. The heat treatment in a hydrogen-containing gas atmosphere of the present invention is performed by treating a predetermined boron-doped silicon wafer with hydrogen gas or Ar,
1000 to 1200 ° C. in a hydrogen-containing gas atmosphere such as a mixed gas of 50% by volume or more of an inert gas such as nitrogen and hydrogen gas.
At a temperature of 30 to 460 minutes, the boron on the surface of the boron-heavy-doped silicon substrate is outwardly diffused, and at least the boron concentration on the outermost surface for epitaxial growth is 1.5 × 10 16 atoms / cm 3. Below.

【0013】本発明の熱処理において「実質的に」と
は、下記及びのいずれかを意味する。即ち、炉内
の昇温速度及び降温速度が極めて速く、ステップ関数的
な熱処理スケジュールを適用できる場合には、例えば、
所定のシリコンウェハをボートにセットして加熱処理炉
に配置し、炉内の雰囲気を水素含有ガス雰囲気としてボ
ロンの外方拡散可能な温度約1100℃で約200分間
以上、約1150℃で約80分間以上、約1200℃で
約30分間以上保持して処理することである。また、こ
の場合の熱処理におけるt秒間熱処理したときのボロン
濃度の深さ方向のプロファイルは次の(1)式:[B
(x,t)]=[BS]+([B0]-[BS])erf(x/2√DTt)(但し、
[B(x,t)]はT℃におけるt秒間熱処理したときのシリ
コン基板最表面からxμmの深さにおけるボロン濃度、
T はT℃におけるボロンの拡散係数(cm2 /秒)で
ある。)で表わされる。
In the heat treatment of the present invention, "substantially" means any of the following. That is, when the rate of temperature rise and rate of temperature drop in the furnace are extremely fast and a step function heat treatment schedule can be applied, for example,
A predetermined silicon wafer is set in a boat and placed in a heat treatment furnace, and the atmosphere in the furnace is set to a hydrogen-containing gas atmosphere at a temperature at which boron can diffuse outwardly at about 1100 ° C. for about 200 minutes or more, and at about 1150 ° C. for about 80 minutes. It is to hold for about 1 minute or more and to hold at about 1200 ° C. for about 30 minutes or more. Further, the profile of the boron concentration in the depth direction when the heat treatment is performed for t seconds in the heat treatment in this case is expressed by the following formula (1): [B
(x, t)] = [B S ] + ([B 0 ]-[B S ]) erf (x / 2√D T t) (However,
[B (x, t)] is the boron concentration at the depth of x μm from the outermost surface of the silicon substrate when heat-treated at T ° C. for t seconds,
D T is the diffusion coefficient of boron at T ° C. (cm 2 / sec). ).

【0014】または、炉内の昇温及び降温に時間を要
する場合は、昇温及び冷却工程におけるボロンの外方拡
散を考慮した熱処理スケジュールを適用する。例えば、
所定のシリコンウェハをボートにセットして加熱処理炉
に配置し、炉内の雰囲気を不活性ガスのみで昇温し、炉
内温度1000℃に到達した時点で炉内を上記水素含有
ガス雰囲気に置換して昇温を続けた後、約1150℃で
約80分間または1200℃で約30分間保持して処理
し、その後、炉内を水素含有雰囲気のまま保持して10
00℃まで温度を降下させ、1000℃以下となった時
点で再び炉内雰囲気を不活性ガスに置換して室温まで冷
却することを意味し、昇温及び冷却工程を含め炉内が1
000℃以上の温度にある時は水素含有ガス雰囲気に保
持することである。この場合の熱処理におけるt秒間熱
処理したときのボロン濃度の深さ方向のプロファイルは
次の(2)式:[B(x,t)]=[BS]+([B0]-[BS])erf(x
/2√∫I FD(T)dt)で表わされる。この式中の∫I FD(T)dt
を、次の(3)式:DT △tT =∫I FD(T)dt によって
熱処理温度T℃の熱処理相当時間△tTに読み替えること
ができる。(但し、[B(x,t)]はT℃におけるt秒間熱
処理したときのシリコン基板最表面からxμmの深さに
おけるボロン濃度、∫I FD(T)dtは熱処理工程における実
質的に熱処理される間、例えば炉内での熱処理工程の1
000℃以上での昇温から冷却までにおけるボロンの拡
散を示し、DT はT℃におけるボロンの拡散係数(cm
2 /秒)であり、△tT は、T℃相当熱処理時間、即
ち、熱処理全工程をT℃で熱処理すると仮定したときに
要する熱処理時間である。)
Alternatively, when it takes time to raise and lower the temperature in the furnace, a heat treatment schedule is applied in consideration of outward diffusion of boron in the heating and cooling steps. For example,
A predetermined silicon wafer is set in a boat and placed in a heat treatment furnace, the atmosphere in the furnace is heated only by an inert gas, and when the temperature in the furnace reaches 1000 ° C., the atmosphere in the furnace is changed to the hydrogen-containing gas atmosphere. After substituting and continuing the temperature rise, the temperature is maintained at about 1150 ° C. for about 80 minutes or 1200 ° C. for about 30 minutes, and then the furnace is kept in a hydrogen-containing atmosphere for 10 minutes.
This means that the temperature is lowered to 00 ° C., and when the temperature becomes 1000 ° C. or less, the atmosphere in the furnace is replaced with an inert gas again and the temperature is cooled to room temperature.
When the temperature is 000 ° C. or higher, it is to be kept in a hydrogen-containing gas atmosphere. In this case, the profile of the boron concentration in the depth direction when the heat treatment is performed for t seconds is expressed by the following formula (2): [B (x, t)] = [B S ] + ([B 0 ]-[B S ]) erf (x
/ 2√∫ I F D (T) dt) ∫ I F D (T) dt in this equation
And the following (3) formula: D T △ t T = ∫ I by F D (T) dt can be read as the heat treatment temperature T ° C. heat treatment time corresponding △ t T. (However, [B (x, t)] is the boron concentration at a depth of x μm from the outermost surface of the silicon substrate when heat-treated at T ° C. for t seconds, ∫ I F D (T) dt is substantially the heat-treatment in the heat-treatment step. During the heat treatment, for example, one of the heat treatment steps in the furnace
It shows the diffusion of boron from the temperature rise above 000 ° C to the cooling, and D T is the diffusion coefficient (cm) of boron at T ° C.
A 2 / sec), △ t T is, T ° C. equivalent heat treatment time, i.e., a heat treatment time required assuming that the heat treatment of the heat treatment the entire process at T ° C.. )

【0015】本発明のエピタキシャルウエハ用シリコン
基板は、上記のようにして所定のシリコンインゴットか
ら形成されるシリコン基板を熱処理して製造することが
できる。得られたエピタキシャルウエハ用シリコン基板
は、内部は本来のボロンヘビードープシリコン基板であ
って、表面ボロン濃度がライトドープに相当するもので
ある。この表面に従来と同様にしてシリコン単結晶をエ
ピタキシャル成長させて所定厚さのエピタキシャル膜を
形成することができる。得られるエピタキシャル膜は、
シリコン基板との界面において結晶格子定数が急激に変
化することがなく、また、ボロン濃度も急変することが
ないため、結晶転位もなく微細構造的な歪みもない、著
しく結晶性の高い欠陥の少ないシリコン単結晶層とな
る。この場合、シリコン基板の熱処理とエピタキシャル
処理とを同一の炉を用いて、熱処理後、直ちにエピタキ
シャル処理することもできる。また、シリコン基板の熱
処理とエピタキシャル処理とをそれぞれ別々の炉を用い
て行ってもよい。処理環境等の各種条件によりいずれの
方式を採用するか選択することができる。なお、キャリ
アドープシリコンウエハを水素ガス、窒素、アルゴン
(Ar)等の雰囲気下で熱処理し表面のドーパント濃度
が変化することは知られている(例えば1995年秋季
・第56回応用物理学会学術講演会・講演予稿集No.
1の第198頁参照)。しかしながら、エピタキシャル
ウエハ用のシリコン基板、特にヘビードープされたシリ
コン基板についてその表面上にシリコン単結晶をエピタ
キシャル成長させるための表面熱処理は現在まで考察さ
れたことがなく発明者らにより初めてなされたものであ
る。
The silicon substrate for an epitaxial wafer of the present invention can be manufactured by heat-treating a silicon substrate formed from a predetermined silicon ingot as described above. The obtained silicon substrate for an epitaxial wafer is an original boron heavy-doped silicon substrate, and the surface boron concentration corresponds to light doping. A silicon single crystal can be epitaxially grown on this surface in a conventional manner to form an epitaxial film having a predetermined thickness. The obtained epitaxial film is
Since the crystal lattice constant does not change sharply at the interface with the silicon substrate and the boron concentration does not change suddenly, there are no crystal dislocations and no microstructural distortion, and there are few defects with extremely high crystallinity. It becomes a silicon single crystal layer. In this case, the heat treatment and the epitaxial treatment of the silicon substrate may be performed in the same furnace, and the epitaxial treatment may be performed immediately after the heat treatment. Further, the heat treatment and the epitaxial treatment of the silicon substrate may be performed using different furnaces. It is possible to select which method is adopted according to various conditions such as a processing environment. It is known that a carrier-doped silicon wafer is heat-treated in an atmosphere of hydrogen gas, nitrogen, argon (Ar), etc. to change the dopant concentration on the surface (for example, Autumn 1995, 56th Annual Meeting of the Applied Physics Society of Japan). Meeting / Lecture Proceedings No.
1 pp. 198). However, the surface heat treatment for epitaxially growing a silicon single crystal on the surface of a silicon substrate for an epitaxial wafer, particularly a heavily-doped silicon substrate, has not been considered until now, and is the first one performed by the inventors.

【0016】[0016]

【実施例】本発明について実施例に基づき、更に詳細に
説明する。但し、本発明は下記の実施例に制限されるも
のでない。本発明の下記実施例において用いた出発シリ
コン基板は、チョクラルスキー法により引き上げられた
シリコン単結晶インゴットを、従来公知の方法でスライ
スし、研磨及び鏡面研磨を施して得られたものである。
これら出発シリコン基板は、ドープボロン濃度3×10
18atoms/cm3 のpタイプ、面方位(100)、
比抵抗が21.4mΩcmであった。
EXAMPLES The present invention will be described in more detail based on examples. However, the present invention is not limited to the following examples. The starting silicon substrate used in the following examples of the present invention is obtained by slicing a silicon single crystal ingot pulled up by the Czochralski method by a conventionally known method and polishing and mirror-polishing it.
These starting silicon substrates have a doped boron concentration of 3 × 10 5.
P type of 18 atoms / cm 3 , plane orientation (100),
The specific resistance was 21.4 mΩcm.

【0017】実施例1 上記の出発シリコン基板を用い、100%水素ガス雰囲
気中で1200℃で2時間の熱処理を行った。先ず出発
シリコン基板を、800℃でArガス雰囲気の炉内に装
入し、800℃から1000℃までを約10℃/分の昇
温速度で昇温し、1000℃となったところで炉内雰囲
気を水素ガス:Arガス=1:1(容量比)の水素含有
混合ガスに置換し、更に1000℃から1100℃まで
を約3℃/分の昇温速度で昇温し、1100℃から熱処
理温度の1200℃までを2℃/分の昇温速度で昇温し
1200℃で2時間保持した。その後、1100℃まで
約3℃/分の降温速度で、800℃まで約4℃/分の降
温速度で冷却した後、炉内雰囲気を不活性ガスに置換し
て100℃/分で室温まで冷却し、熱処理したシリコン
基板を得た。得られた熱処理シリコン基板におけるボロ
ン濃度と表面からの深さとの関係をSIMS(二次イオ
ン質量分析法)を用いて測定した。その結果を図3にA
として示した。
Example 1 Using the above starting silicon substrate, heat treatment was performed at 1200 ° C. for 2 hours in a 100% hydrogen gas atmosphere. First, the starting silicon substrate is charged into a furnace in an Ar gas atmosphere at 800 ° C., the temperature is raised from 800 ° C. to 1000 ° C. at a heating rate of about 10 ° C./min, and when the temperature reaches 1000 ° C., the atmosphere in the furnace is reached. Is replaced with a hydrogen-containing mixed gas of hydrogen gas: Ar gas = 1: 1 (volume ratio), and the temperature is further raised from 1000 ° C. to 1100 ° C. at a heating rate of about 3 ° C./min. Up to 1200 ° C. at a temperature rising rate of 2 ° C./min and held at 1200 ° C. for 2 hours. Then, after cooling to 1100 ° C. at a cooling rate of about 3 ° C./min and to 800 ° C. at a cooling rate of about 4 ° C./min, the atmosphere in the furnace was replaced with an inert gas and cooled to room temperature at 100 ° C./min. Then, a heat-treated silicon substrate was obtained. The relationship between the boron concentration and the depth from the surface of the obtained heat-treated silicon substrate was measured using SIMS (secondary ion mass spectrometry). The result is shown in Fig. 3A.
As shown.

【0018】比較例1 実施例1と同様に上記出発シリコン基板を炉内雰囲気を
Arガスのままとした以外は実施例1と同様に熱処理し
た。得られた熱処理シリコン基板のボロン濃度と表面か
らの深さとの関係を、同様にSIMSで測定した。その
結果を図3にBとして示した。なお、図3に、出発シリ
コン基板を同様にSIMSで測定した結果をCとして示
した。図3により明らかなように表面ボロン濃度が2×
1016atoms/cm3 以下に低減し、ほぼ2μmの
深さまで逓増し、その後徐々に初期のボロン濃度へ増加
していることが分かる。一方、Arガス雰囲気での熱処
理ではドープボロンが減少しないことが分かる。
Comparative Example 1 Similar to Example 1, the starting silicon substrate was heat-treated in the same manner as in Example 1 except that the atmosphere in the furnace was Ar gas. The relationship between the boron concentration and the depth from the surface of the obtained heat-treated silicon substrate was similarly measured by SIMS. The result is shown as B in FIG. In addition, in FIG. 3, the result of having measured the starting silicon substrate similarly by SIMS is shown as C. As is clear from FIG. 3, the surface boron concentration is 2 ×
It can be seen that the concentration is decreased to 10 16 atoms / cm 3 or less, the depth is gradually increased to about 2 μm, and then the boron concentration is gradually increased to the initial concentration. On the other hand, it is understood that the doped boron is not reduced by the heat treatment in the Ar gas atmosphere.

【0019】実施例2〜5 水素ガス雰囲気下、炉内温度を1000℃、1100
℃、1150℃及び1200℃にそれぞれ保持し、各炉
内で上記出発シリコン基板を、それぞれ10分、30
分、60分、100分、200分、300分、400
分、500分及び600分間処理した。得られた各熱処
理シリコン基板について、実施例1と同様にSIMSで
ボロン濃度と表面深さとの関係を測定し、出発シリコン
基板の初期ボロン濃度3×1018atoms/cm3
([B0 ])の90%のボロン濃度値([B0.9 ])を
示す深さ(μm)を算出し、各熱処理温度における[B
0.9 ]と処理時間の関係を図4に示した。これらの結果
から、表面から2μmの深さで[B0.9 ]に到達するを
各熱処理温度での所要熱処理時間が分かる。例えば12
00℃であれば、約30分、1150℃であれば約75
分、1100℃では200分を要することが明らかであ
る。
Examples 2 to 5 In a hydrogen gas atmosphere, the temperature inside the furnace was 1000 ° C. and 1100.
C., 1150.degree. C. and 1200.degree. C., respectively, and the starting silicon substrate is placed in each furnace for 10 minutes and 30 minutes, respectively.
Minutes, 60 minutes, 100 minutes, 200 minutes, 300 minutes, 400
Min, 500 min and 600 min. For each of the obtained heat-treated silicon substrates, the relationship between the boron concentration and the surface depth was measured by SIMS in the same manner as in Example 1, and the initial boron concentration of the starting silicon substrate was 3 × 10 18 atoms / cm 3.
A depth (μm) showing a boron concentration value ([B 0.9 ]) of 90% of ([B 0 ]) was calculated, and [B at each heat treatment temperature was calculated.
0.9 ] and the processing time are shown in FIG. From these results, it can be seen that the required heat treatment time at each heat treatment temperature to reach [B 0.9 ] at a depth of 2 μm from the surface. For example, 12
About 30 minutes at 00 ° C, about 75 minutes at 1150 ° C
It is clear that at 1100 ° C, it takes 200 minutes.

【0020】実施例6及び比較例2 実施例1で得られた熱処理シリコン基板(実施例6)及
び上記出発シリコン基板(比較例2)上にそれぞれ、原
料ガスとしてSiH2 Cl2 を用い、1080℃で5分
間処理して、シリコン単結晶膜を約5μmの厚さにエピ
タキシャル成長させ、それぞれエピタキシャルウエハを
得た。得られたエピタキシャルウエハについてSIMS
で、表面から深さ方向のボロン濃度を測定して観察し
た。図5に比較例2の結果をに示した。この結果から従
来のヘビーボロンドープのシリコン基板上に形成された
エピタキシャルシリコン膜は、シリコン基板との界面で
約0.1μmの幅で急激にボロン濃度が変化しているこ
とが分かる。一方、本発明の熱処理したシリコン基板上
では約2μmの幅で緩やかな勾配でボロン濃度が内部方
向に増加していくことが観察された。
Example 6 and Comparative Example 2 SiH 2 Cl 2 was used as a source gas on the heat-treated silicon substrate (Example 6) obtained in Example 1 and the starting silicon substrate (Comparative Example 2), respectively. After processing at 5 ° C. for 5 minutes, a silicon single crystal film was epitaxially grown to a thickness of about 5 μm to obtain an epitaxial wafer. SIMS of the obtained epitaxial wafer
Then, the boron concentration in the depth direction from the surface was measured and observed. The results of Comparative Example 2 are shown in FIG. From this result, it can be seen that the epitaxial silicon film formed on the conventional heavy boron-doped silicon substrate has a rapid boron concentration change with a width of about 0.1 μm at the interface with the silicon substrate. On the other hand, it was observed that on the heat-treated silicon substrate of the present invention, the boron concentration increased inward in a width of about 2 μm with a gentle gradient.

【0021】[0021]

【発明の効果】本発明のエピタキシャルウエハ用シリコ
ン基板は、その内部はヘビーボロンドープを保持しつ
つ、エピタキシャル成長させる最外表面のボロン濃度が
エピタキシャルシリコン単結晶膜のライトボロンドープ
濃度にほぼ相当するように低減されると共に内部方向に
逓増してヘビードープのボロン濃度となることから、シ
リコン単結晶をエピタキシャル成長させて得られるエピ
タキシャルウエハは、エピタキシャル膜とシリコン基板
との界面で結晶格子定数の歪みの発生が無く、微細な構
造的欠陥も無い良好なエピタキシャルシリコン単結晶表
面を有する。そのため良好なデバイス形成領域が確保さ
れ、最終的にはその上に形成される素子に欠陥を生じる
ことなく優れた素子特性を有する超LSIを、歩留よく
製造でき、信頼性も向上させることができる。
EFFECTS OF THE INVENTION The silicon substrate for an epitaxial wafer of the present invention is such that the boron concentration of the outermost surface on which epitaxial growth is performed substantially corresponds to the light boron doping concentration of the epitaxial silicon single crystal film while maintaining the heavy boron doping inside. In addition, the epitaxially-doped epitaxial wafer obtained by epitaxially growing a silicon single crystal is free from the occurrence of distortion of the crystal lattice constant at the interface between the epitaxial film and the silicon substrate, since It has a good epitaxial silicon single crystal surface without any fine structural defects. Therefore, a good device formation region can be secured, and ultimately, a VLSI having excellent device characteristics without causing defects in the device formed thereon can be manufactured with high yield and reliability can be improved. it can.

【図面の簡単な説明】[Brief description of drawings]

【図1】ライトドープシリコン基板のラマンスペクトルFIG. 1 Raman spectrum of lightly doped silicon substrate

【図2】ヘビードープシリコン基板のラマンスペクトルFIG. 2 Raman spectrum of heavy-doped silicon substrate

【図3】本発明の実施例で得られた水素雰囲気熱処理シ
リコン基板(A)、比較例で得られたアルゴン雰囲気熱
処理シリコン基板(B)及び熱処理前の出発シリコン基
板(C)についてのSIMS分析結果
FIG. 3 is a SIMS analysis of a hydrogen atmosphere heat treated silicon substrate (A) obtained in an example of the present invention, an argon atmosphere heat treated silicon substrate (B) obtained in a comparative example, and a starting silicon substrate (C) before heat treatment. result

【図4】ボロン濃度値([B0.9 ])と熱処理温度にお
ける処理時間との関係図
FIG. 4 is a relational diagram between a boron concentration value ([B 0.9 ]) and a treatment time at a heat treatment temperature.

【図5】従来のヘビーボロンドープのシリコン基板表面
にシリコン単結晶をエピタキシャル成長させて製造した
エピタキシャルウエハのSIMS分析結果
FIG. 5: SIMS analysis results of an epitaxial wafer manufactured by epitaxially growing a silicon single crystal on the surface of a conventional heavy boron-doped silicon substrate.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 林 健郎 神奈川県秦野市曽屋30番地 東芝セラミッ クス株式会社開発研究所内 (72)発明者 吉川 淳 神奈川県秦野市曽屋30番地 東芝セラミッ クス株式会社開発研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenro Hayashi, 30 Soya, Hadano City, Kanagawa Prefecture, Toshiba Ceramics Co., Ltd.Development Research Laboratory (72) Inventor, Jun 30, Soya, Hadano City, Kanagawa In-house

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 所定にヘビードープされたボロン濃度
[B0 ]を有するシリコン基板であって、該基板のエピ
タキタシャル膜を成長させる最表面における表面ボロン
濃度[BS ]が1.5×1016atoms/cm3 以下
であり、且つ、[B0 ]×0.5以上のボロン濃度[B
X ]まで該最表面から少なくとも2μmの深さに亘りボ
ロン濃度が勾配を有して逓増することを特徴とするエピ
タキシャルウエハ用シリコン基板。
1. A silicon substrate having a predetermined heavy-doped boron concentration [B 0 ] having a surface boron concentration [B S ] of 1.5 × 10 5 at the outermost surface on which an epitaxial film is grown. A boron concentration of 16 atoms / cm 3 or less and [B 0 ] × 0.5 or more [B
X ]], wherein the boron concentration has a gradient and gradually increases from the outermost surface to a depth of at least 2 μm.
【請求項2】 前記ボロン濃度[B0 ]が1×1017
toms/cm3 以上である請求項1記載のエピタキシ
ャルウエハ用シリコン基板。
2. The boron concentration [B 0 ] is 1 × 10 17 a
The silicon substrate for an epitaxial wafer according to claim 1, which has a thickness of toms / cm 3 or more.
【請求項3】 所定にヘビードープされたボロン濃度
[B0 ]を有するシリコン基板のエピタキタシャル膜を
成長させる表面を、水素含有ガス雰囲気下で熱処理し、
少なくとも最表面ボロン濃度[BS ]を1.5×1016
atoms/cm3 以下とすることを特徴とするエピタ
キシャルウエハ用シリコン基板の製造方法。
3. A surface of a silicon substrate having a predetermined heavy-doped boron concentration [B 0 ] on which an epitaxial film is to be grown is heat-treated in a hydrogen-containing gas atmosphere,
At least the outermost surface boron concentration [B S ] is 1.5 × 10 16
A method of manufacturing a silicon substrate for an epitaxial wafer, which is characterized in that it is not more than atoms / cm 3 .
【請求項4】 前記水素含有ガスが、水素ガスとアルゴ
ンガスが容量比H2/Ar>1の混合ガスである請求項
3記載のエピタキシャルウエハ用シリコン基板の製造方
法。
4. The method for producing a silicon substrate for an epitaxial wafer according to claim 3, wherein the hydrogen-containing gas is a mixed gas of hydrogen gas and argon gas having a volume ratio of H 2 / Ar> 1.
【請求項5】 前記熱処理が、実質的に水素含有ガス雰
囲気において1000〜1200℃の温度で30〜46
0分間の処理時間で行なわれる請求項3または4記載の
エピタキシャルウエハ用シリコン基板の製造方法。
5. The heat treatment is performed in a hydrogen-containing gas atmosphere at a temperature of 1000 to 1200 ° C. for 30 to 46.
The method for producing a silicon substrate for an epitaxial wafer according to claim 3, which is carried out for a processing time of 0 minutes.
【請求項6】 前記処理時間が、次式:DT △tT =∫I F
D(T)dt(但し、∫I FD(T)dtは、熱処理工程における熱処
理開始から熱処理終了まで(実質的に1000℃以上で
の昇温から冷却工程を含む)のボロンの拡散を示し、D
T はT℃におけるボロンの拡散係数(cm2 /秒)であ
り、△tT はT℃相当熱処理時間、即ち、熱処理全工程
をT℃で熱処理すると仮定したときに要する熱処理時間
である。)で表わされる△tT である請求項5記載のエ
ピタキシャルウエハ用基板の製造方法。
Wherein said processing time, the following equation: D T △ t T = ∫ I F
D (T) dt (where, ∫ I F D (T) dt represents the diffusion of boron to completion of the heat treatment from the start of the heat treatment in the heat treatment step (including a substantially cooling process from Atsushi Nobori at 1000 ° C. or higher) , D
T is a boron diffusion coefficient (cm 2 / sec) at T ° C., and Δt T is a T ° C. equivalent heat treatment time, that is, a heat treatment time required when it is assumed that all heat treatment steps are performed at T ° C. 6. The method for manufacturing an epitaxial wafer substrate according to claim 5, wherein Δt T is represented by
JP2216196A 1996-01-12 1996-01-12 Si substrate for epitaxial wafer and its manufacturing method Pending JPH09199380A (en)

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Country Link
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US6667522B2 (en) * 1999-09-22 2003-12-23 Intel Corporation Silicon wafers for CMOS and other integrated circuits
JP2007266125A (en) * 2006-03-27 2007-10-11 Covalent Materials Corp Silicon epitaxial wafer and manufacturing method therefor
JP2010098284A (en) * 2008-09-19 2010-04-30 Covalent Materials Corp Method for production of silicon wafer for epitaxial substrate, and method for production of epitaxial substrate
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6667522B2 (en) * 1999-09-22 2003-12-23 Intel Corporation Silicon wafers for CMOS and other integrated circuits
JP2002190478A (en) * 2000-12-22 2002-07-05 Komatsu Electronic Metals Co Ltd Method for heat-treating boron-doped silicon wafer
JP2007266125A (en) * 2006-03-27 2007-10-11 Covalent Materials Corp Silicon epitaxial wafer and manufacturing method therefor
JP2010098284A (en) * 2008-09-19 2010-04-30 Covalent Materials Corp Method for production of silicon wafer for epitaxial substrate, and method for production of epitaxial substrate
CN101710566A (en) * 2008-09-19 2010-05-19 科发伦材料株式会社 Method for production of silicon wafer for epitaxial substrate and method for production of epitaxial substrate
US8216921B2 (en) 2008-09-19 2012-07-10 Covalent Materials Corporation Method for production of silicon wafer for epitaxial substrate and method for production of epitaxial substrate
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