JPS6358800B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field The present invention relates to a method for improving the uniformity of the axial properties of GaAs single crystal ingots and achieving this with good reproducibility between ingots. (a) Conventional technology GaAs single crystal is manufactured by horizontal Bridgeman method (HB)
Alternatively, it is often manufactured using the liquid capsule method (LEC). The manufactured single crystal ingot contains many crystal defects. Defects are often evaluated using etched pit density (EPD). The ingot is sliced into wafers, which are etched and the etch pits that appear on the surface are counted to evaluate the degree of defects contained in the single crystal. Etchi pits are dislocations that appear on the cut surface of the wafer, and are therefore a measure of lattice defects. Although the LEC method and the HB method are industrially superior methods, single crystals produced by these methods often still have many defects. For example, in the case of a GaAs single crystal with a diameter of 50 mm or more made by the LEC method,
The EPD ranges from ¹⁰⁴ cm ^-2 to 5× ¹⁰⁵ cm ^-2 . Furthermore, the tips are unevenly distributed.
Even when viewed within the wafer plane, it is most common at the outer periphery, followed by the center. The distance from the center will be less. It has a W-shaped distribution. This is a problem of the in-plane chip distribution. Added to this is the axial non-uniformity of the ingot. In the case of single crystals made by the LEC method, the EPD is relatively low at the front near the seed crystal, but increases as the distance from the seed crystal increases. Field-effect transistors (FETs) can be made from GaAs single-crystal wafers. In this case, the threshold voltage Vth, which determines whether switching is turned on or off, becomes an important parameter. Although it is desirable that Vth be constant, it is normal that it fluctuates even within a wafer. It has been pointed out that there is a strong correlation between the non-uniformity of the threshold voltage Vth and the distribution of EPD. For example, Miyazawa et al. Applied Physics Vol. 52 No. 3 (1983)
Page 227 describes the correlation between Vth and EPD. As with EPD, non-uniformity in Vth includes non-uniformity within the wafer plane and non-uniformity across the wafer in the axial direction of the ingot. Although reducing dislocations is not completely equivalent to reducing variations in Vth, it is possible to improve uniformity and reduce variations in threshold voltage Vth by reducing dislocations. Annealing has been attempted to improve the uniformity of the crystal. In some cases, the wafer is made into a wafer and then annealed. This is called wafer annealing. In some cases, the ingot is annealed. This is called ingot annealing. Since group elements in single crystals of - group compound semiconductors tend to dissociate at high temperatures, it is necessary to take measures to prevent group V elements from escaping during annealing. For this reason, a film is sometimes attached to the wafer or ingot and annealed in this state. Annealing may be performed in a group V gas to balance the partial pressure of the group V gas and prevent volatilization of group elements. Alternatively, annealing may be performed by applying high pressure with nitrogen gas or the like. There is a report that wafer annealing reduces the variation in Vth within the wafer surface. The direct objective of ingot annealing is to improve uniformity on the wafer surface. This is because a large number of integrated circuits are manufactured on a wafer, and variations in the characteristic values of the unit integrated circuits often become a problem. Therefore, even in the case of ingot annealing, the aim was not to improve the uniformity in the axial direction of the ingot. Therefore, in the case of ingot annealing, the pulled crystal is not annealed as it is, but is often cut into small rings and annealed. This is because there are restrictions on the size of the container for annealing, and since a coating is sometimes applied to the surface, ingots that are small in size and have a uniform shape are easier to handle. Here, we will define the term axial direction.
In the case of a crystal grown using the LEC method, the upper and lower axes are vertical, and the crystal also extends in the vertical direction. The direction in which the crystal grows is the axial direction. When an ingot is sliced perpendicularly to the axis to form a wafer, the wafer surface is perpendicular to the axis. However, the wafer is not necessarily cut perpendicular to the axis. In this case, the distribution on the wafer surface and the distribution in the axial direction are not distributions between orthogonal axes. However, since wafers are always sliced along their axis, it is always possible to distinguish between the planar direction and the axial direction. In the case of ingots made by the HB method, the axial direction is the direction along the boat. Since wafers are often cut obliquely to the axis, the wafer surface direction and the axis direction are often not perpendicular. However, in any case, a distinction can be made. To identify the location in the axial direction, the side closest to the seed crystal is called the front part, and the side opposite to the seed crystal is called the back part. The middle part will be called the middle part. Furthermore, since the surfaces appear only when the ingot is cut in a certain direction, the surfaces do not exist before the ingot is cut. When annealing is performed as an ingot, the plane direction refers to a plane that does not yet exist. However, since the direction of the plane to be cut is known, the term plane direction itself can be sufficiently defined. Therefore, in the description of the present invention, the term surface direction is used even in the ingot state, but this does not mean that this surface already exists somewhere. (c) Purpose It is an object of the present invention to provide a GaAs single crystal annealing method for producing a single crystal with uniform electrical properties not only in the plane direction but also in the axial direction. (d) Method of the present invention The method will be explained using semi-insulating undoped LEC GaAs as an example. This is to be used as a FET substrate. Inside a GaAs single crystal, there is a deep impurity level called "EL2" and a shallow impurity level (sometimes a donor level or an acceptor level). The uniformity of the microscopic and macroscopic distribution of these two impurity levels governs the electrical uniformity of the GaAs single crystal. Macroscopically, the concentration of the "EL2" level has a W-shaped distribution within the wafer plane, and has four-fold symmetry. This corresponds well to the macroscopic density distribution of dislocations, which are a type of crystal defect. For this reason,
Macroscopically, the distribution of electrical properties such as resistivity and carrier mobility also exhibits four-fold symmetry with a W-shaped distribution (or inverse W-shaped distribution). This is explained by DE Holmes et al. “Contour
maps of EL2 deep level in liquid−
encapsulated Czochralski GaAs”J.Appl.Phys.
55 (1984) pp3588. The “EL2” concentration has variations in the axial and surface directions of the ingot. Furthermore, there are large variations in concentration and distribution between ingots. Variations in EL2 concentration are the cause of non-uniformity in electrical characteristics. On the other hand, the occurrence of dislocations depends on the thermal environment that the crystal receives during growth or cooling. In other words, the dislocation density distribution is considered to represent the thermal hysteresis experienced by the crystal. The origin of “EL2” is “aggregation of As”
(EL2Family) theory is becoming popular. this is,
M. Taniguchi et al. “Spectral distribution of
photoquenching rate and multistable states
for midgap electron traps (EL2family) in
GaAs” Appl. Phys. Lett. 45 , 69 (1984). There is still no definitive theory about the origin of EL2, and there is also a theory that it is created by oxygen atoms, and that GaAs is substituted with As. There is also a theory that it is a level formed by As. It has been reported that by ingot annealing, the number of "EL2" does not decrease, but the distribution becomes uniform. D. Rumsby et al. “IMPROVED
UNIFORMITY OF LEC UNDOPED
GALLIUM ARSENIDE PRODUCED BY
HIGH TEMPERATURE ANNEALING”
GaAs IC Symposium (1983) IEEE p.34~
p.37. According to this, in the temperature range of 700℃~1000℃
Annealing the GaAs ingot for ~60 hours yields
This means that the EL2 concentration becomes uniform and becomes about 12×10 ¹⁵ cm ^-3 . The relationship between dislocation and EL2 is not simple. In the case of a dislocation-free crystal, the EL2 concentration is uniform and low, about 4×10 ¹⁵ cm ^-3 . The EPD made by the Bridziman method is about 10 ⁴ cm ^-2.
GaAs has an EL2 concentration of about 12×10 ¹⁵ cm ^-3 like LEC GaAs. In other words, the amount of dislocations and the concentration of EL2 are not proportional. However, in dislocation-free (In-doped LEC) GaAs, the EL2 concentration is about 1/3. When these ingots are annealed in an inert gas under the above conditions, the distribution of EL2 becomes uniform. Moreover, the concentration becomes 12×10 ¹⁵ cm ^-3 . No dislocation
For GaAs crystals, this means that the EL2 concentration increases by a factor of three upon annealing. For both LECGaAs and HB GaAs, before annealing
The EL2 concentration has a W distribution and has 4-fold symmetry. In In-doped dislocation-free GaAs, the EL2 concentration is low and uniform. When these ingots are annealed, the EL2 concentration becomes uniform in all ingots.
The W distribution disappears and the 4-fold symmetry is no longer observed.
Moreover, the EL2 concentration of any ingot is approximately the same, 12×10 ¹⁵ cm ^-3 . However, dislocations are unchanged by annealing.
Dislocations do not disappear, decrease, or increase. It has already been mentioned that the value of the threshold voltage Vth, which determines the electrical characteristics of the FET, depends on the distribution of EL2.
This does not depend solely on the distribution of EL2, but this seems to have a strong correlation. The magnitude of the concentration of EL2 is not very important, but the fluctuation of the concentration is the problem. The dislocation density of an ingot changes both in the planar and axial directions. Similarly, the EL2 distribution also fluctuates in the planar and axial directions. If the ingot contains dislocation-free portions, the average value of the EL2 concentration will also vary in the axial direction. Since the EL2 concentration has a strong relationship with the threshold voltage when used as an FET, an FET is placed on a wafer cut from such an ingot.
When creating a wafer, the threshold voltage varies not only within the wafer but also between wafers. A wafer taken from the front part of the ingot and a wafer taken from the back part have vertically different distributions of threshold voltage across the wafer surface. However, as mentioned above, when the GaAs ingot is annealed, the EL2 concentration distribution becomes flat and
Moreover, regardless of the level of EPD before annealing,
It has been reported that the average value of EL2 concentration remains almost constant. This is strange. Annealing does not reduce EPD. Also, the etchipite has a four-fold symmetry. This symmetry is not lost even after annealing. Before annealing, the EL2 concentration has a W-shaped distribution similar to that of the etching pit, and has a 4-fold symmetry. However, due to ingot annealing, only the EL2 concentration loses its W-shaped distribution and the 4-fold symmetry. This experiment is not necessarily reliable because the amount of data is small. However, it seems to make it clearer that there is no direct relationship between EL2 and EPD concentrations. As mentioned above, the measurement of EL2 concentration has been carried out by many researchers, and there are various theories regarding its origin. The theory of "aggregation of As" seems to be the most likely, but this is also not conclusive. Therefore, the present inventor temporarily cooled the single crystal after crystal growth to a temperature of 450°C to 550°C without cooling it to room temperature, and then heated it to 700°C in an inert gas or vacuum. We came up with a method of heat treatment at a temperature range of ~1000℃ for 6 to 60 hours. The latter half of the annealing is publicly known,
Atmosphere, temperature, and time have already been tried. The first stage of processing is new. This is to form a deep impurity level "EL2" throughout the crystal ingot. Regardless of the LEC method or the HB method, after a single crystal is grown, it is gradually cooled down to room temperature and taken out of the furnace. In other words, it will soon reach room temperature. If you don't do this, you won't be able to perform the necessary processing. Even though it is called ingot annealing, it does not mean that the entire ingot is annealed. Since the container is very restrictive, it is sliced into several pieces, placed in a capsule, and heated in a vacuum or in a nitrogen or argon gas atmosphere. However, when you do this, you always have to bring it down to room temperature. The inventor thought that at this time, the EL2 distribution would occur non-uniformly in the axial direction of the ingot. The temperature distribution during the cooling process in the furnace is not uniform in the axial direction. Due to the location of the heaters, the first part of the ingot to solidify is at a low temperature, and the last part to solidify is at a high temperature. Since the temperature decreases in such a non-uniform temperature, the amount of generated EL2 level varies greatly in the axial direction. In the present invention, cooling is not lowered to room temperature, cooling is stopped midway, and annealing is performed in the same furnace.
The aim is to make the generation of the EL2 level more uniform from the beginning. Since the annealing is performed in the same furnace, this furnace doubles as a crystal growth furnace and an annealing device. The reason why the temperature is lowered to a range of 450°C to 550°C is to generate the EL2 level here. The purpose of annealing next is to redistribute the EL2 levels created in this way and make them uniform. Lowering the temperature below 450°C is undesirable because it causes uneven generation of EL2. Unequal means
This means in the axial direction, not in the planar direction. As mentioned above, intrinsic defects such as vacancies and interstitial atoms are largely involved in the formation of EL2. The concentration, morphology, etc. of intrinsic defects reach their thermal equilibrium state at a certain temperature. Generally, the higher the temperature, the higher the concentration of intrinsic defects, and the lower the temperature, the lower the concentration. In other words, when the solidified crystal is cooled from a high temperature, the intrinsic defects in excess of the thermal equilibrium concentration are precipitated,
Or change into another form. This process of change is not necessarily reversible from a thermal point of view. The intrinsic defects that contribute to EL2 formation are in a thermally reversible process above 450°C, but when cooled below 450°C, the irreversible process becomes larger. This leads to an uneven distribution of EL2. Therefore, it is important not to lower the temperature below 450°C once the crystals have solidified. This point differs from the conventional method, which involves simply lowering the temperature to room temperature. Unless the temperature is lowered to below 550°C, the EL2 level will not be formed in the crystal. This is because the inherent defects that form EL2 are not generated unless the temperature of the crystal, once solidified, is lowered to below 550°C. However, once EL2 is formed, its form does not change unless the temperature is above 700°C, as described below. If the EL2 level is not present in the crystal, it cannot be redistributed by annealing. Regarding the annealing temperature, if it is set to 1000°C or higher, the group elements will be violently dissociated from the crystal surface, which will deteriorate the properties of the crystal. Furthermore, if the temperature is below 700°C, redistribution of the EL2 level does not occur. (E) Example The method of the present invention was applied to a low chromium-doped semi-insulating GaAs crystal grown by the LEC method. For comparison, the method of the present invention is not applied.
They also made GaAs crystals. It is necessary to investigate the axial electrical properties of one ingot, as well as the differences in electrical properties between ingots. For this reason, seven ingots were made and their properties were compared. Since the variation in the threshold voltage Vth was to be compared, the ingot was used as a wafer, an n region was formed thereon, an electrode was attached thereto, the CV characteristics were measured, and the pinch-off voltage _Vp was determined. The GaAs single crystal to which the method of the present invention was applied was first cooled to 450°C to 550°C. This is done inside the LEC device. The temperature of the crystal during cooling differs considerably between the top and bottom, but the difference in temperature between the top and bottom can be reduced by providing an insulating tube surrounding the cooling zone or by using an after-heating heater. The seven ingots are numbered No. 1 to No. 7. (1) No.1 and No.2 are annealed at 700℃ for 6 hours (2) No.3 and No.4 are annealed at 700℃ for 12 hours (3) No.5 and No.6 are annealed at 800℃ for 6 hours Annealing (4) For No. 7, the temperature and time were set to be annealing at 800°C for 12 hours. this is
Since this is carried out using an LEC device, another annealing heater is provided at or above the position where the crystal is pulled up and cooled, and the crystal is heated by this. This can also be used as the above-mentioned after-heater. In this case, although the crystal is vertically long, the length, position, or number of the heaters are set so that the temperatures at the top and bottom are the same. Seven ingots that were heat-treated in this way,
Measure the pinch-off voltage V _p of the other seven ingots that have not been heat treated. The procedure for measuring this is well known and all procedures are the same. Take out the ingot from the LEC device. Take out one sample from the front section and one sample from the back section. All ingots have a diameter of 55mm (55±3
mm), and the length is approximately 50 mm. The front sample was cut out 10 mm from the top of the crystal. The back sample was cut out 40mm from the top edge (10mm from the bottom edge). The sliced wafer is subjected to normal processing to become a mirror wafer. That is, it is made into a mirror surface through the processes of beveling, etching, wrapping, etching, and polishing. This wafer is semi-insulating, but contains Si ions.
Ions were implanted at a density of 3×10 ¹² cm ⁻² under acceleration of 180 KeV to form an n-type layer. Furthermore, the SiO ₂ film was deposited at 2000 to 3000 using the CVD method.
Å was deposited, and annealing was performed at 820°C for 20 minutes in a nitrogen atmosphere. This is to activate the implanted impurities and restore the lattice structure. This is always performed after ion implantation, and unlike ingot annealing, it does not reduce variations in electrical characteristics and takes a short time. After this, the SiO ₂ film is removed. Deposited gold, diameter
A large number of Schottky electrodes with a diameter of 200 μm were formed on the active layer. CV measurement was performed using this electrode. Second
A CV curve as shown in the figure is obtained. The voltage V _p at which the slope of C with respect to V becomes large was defined as the pinch-off voltage V _p . Such data was obtained for many points on the wafer. The average value of this voltage is defined as the pinch-off voltage V _p of this wafer. Wafers of the front part (S) and the back part (T) are cut out from seven ingots. The average value of this pinch-off voltage on the wafer is shown in Figure 1a.
Shown below. The horizontal axis is the wafer number. S is for front;
T corresponds to the wafer taken from the back. The vertical axis is the pinch-off voltage V _p . FIG. 1a shows, as white circles, the average pinch-off voltage for wafers taken from ingots that have been cooled and annealed according to the present invention. In order to easily show the correspondence, the annealing temperature and annealing time are written directly below it. Pinch-off voltage is −4.1 to −5.4V
It's between. For comparison, seven ingots No. 8 to No. 14 to which the method of the present invention was not applied were similarly made into mirror wafers, doped with Si to form an active layer, and
Pinch-off voltage was measured. The results are shown in Figure 1b. S is a wafer cut from the front, and T is a wafer cut from the back. Similarly, the pinch-off voltage V _p is measured at a large number of measurement points on the wafer, and the average value is calculated. This is shown as a black circle, and the pinch-off voltage is −
It is between 3.8V and -6.43V. It can be seen that the pinch-off voltage V _p of the n-layer made from the ingot improved by the method of the present invention has less variation. From No. 1, No. 5, No. 6, etc., it becomes clear that the difference between the front and back of V _p is decreasing. What is surprising is that the difference in V _p between ingots becomes smaller. There is a difference in pinch-off voltage of about 2.6V between No. 9 and No. 11 to which the method of the present invention was not applied. On the other hand, among those to which the present invention is applied, No. 2
No. 7 has the largest difference, but it is still only 1.3V. (f) Effects (1) A single crystal with uniform electrical properties can be produced in the axial direction of the ingot. (2) Electrical characteristics can be made almost uniform between different ingots. Since the electrical characteristics are stable from one ingot to another, FET substrate materials can be made with good reproducibility.

[Brief explanation of the drawing]

Figure 1a shows a Cr-doped sample made by the method of the present invention.
The figure shows the average value of the pinch-off voltage in the front part S and back part T of a GaAs ingot with white circles. There were seven ingots, numbered No. 1 to No. 7. The annealing conditions are listed below.
Figure 1b shows seven Cr-doped GaAs made using the conventional method.
It is a diagram in which the average value of the pinch-off voltage at the front part S and back part T of the ingot is shown by black circles. The ingots were numbered No. 8 to No. 14.
FIG. 2 is a graph explaining the method of determining the pinch-off voltage V _p from the CV curve.

Claims (1)

[Claims] 1 Cool the GaAs single crystal ingot after crystal growth to a temperature of 450°C to 550°C in a crystal growth apparatus,
After this, 700 minutes in an inert gas atmosphere or vacuum.
It has uniform properties characterized by heat treatment in the temperature range from ℃ to 1000℃ for 6 hours or more and 60 hours or less.
Method of manufacturing GaAs single crystal.