JPS61283162A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To highly integrate a semiconductor memory device by longitudinally providing rows of word decoders and word line drivers laterally of a memory matrix, and constructing to run word lines alternately from the right and left word line drivers on a memory matrix. CONSTITUTION:Word decoders 101, 102 and word line drivers 201, 202 are formed along the bit line 40 of a memory matrix 30. The word lines 50 corresponding to the outputs of the drivers 201, 202 run alternately on a memory matrix 30 from the right and left word line drivers 201, 202. That is, two word lines are disposed in a drive pitch for generating one word line output, the pitches of the decoders 101, 102 and the drivers 201, 202 are doubled by the pitch of the memory cell 60, i.e., the pitch of the word line 50, thereby reducing the interval between the word lines.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to a semiconductor memory device that enables large capacity and high integration.

[Background technology of the invention]

As semiconductor memory devices become larger in storage capacity and more highly integrated, there is a need to reduce the size of memory cells that constitute the memory devices. As the size of the memory cells decreases, the spacing between word lines provided along the memory cells also decreases, and therefore the size of the driver circuit for driving the word lines must also decrease. However, the word line driver circuit is
Since the circuit is more complex than that of a memory cell, its size cannot be reduced beyond a certain point. Moreover, since the structure is such that one word line is installed for each word line driver circuit pitch, the size of the word line driver circuit sets the limit for the word line spacing. However, this results in hindering the reduction of the memory cell portion.

In order to solve this problem, for example, the means shown in Japanese Utility Model Publication No. 57-25440 has been considered. That is, word line driver circuits are provided in two rows along the bit line direction, with a decoder circuit sandwiched in the semiconductor substrate constituting the memory device, and a large number of word lines are formed to extend on both sides of the word line driver circuits. It is something that exists. In this way, two pitches are included within one pitch of the driver circuit.
The memory size can be reduced by making it possible to arrange a book's word line9. However, with such means, the word line crosses over the decoder circuit and the word line driver circuit, which complicates the baton design.

It has also been considered to arrange two word lines of the same signal, which are output from the word line driver circuit, for each word line driver circuit pitch, thereby making it possible to reduce the word line spacing.

However, with this method, memory cells can only be placed at the intersections of every other bit line with respect to each word line, so there is a drawback in terms of integration that the length of the word line becomes long.

[Problems to be solved by the invention]

This invention has been made in view of the above points, and is designed to meet the reduction rate of memory cell size due to high integration.
It is an object of the present invention to provide a semiconductor memory device configured with a button design that allows easy downsizing of the entire semiconductor device including a decoder circuit, a word line driver circuit, and the like.

[Means for solving problems]

That is, in the semiconductor memory device according to the present invention, rows of word decoder circuits and word line driver circuits are vertically provided on the left and right sides of a memory matrix, and the word lines run alternately on the memory matrix from the left and right word line driver circuits. The pitch of the word line driver circuit is twice the pitch of the memory cells to achieve high integration.

[Effect]

In a semiconductor memory device configured in this manner, word lines with different signals alternately run from the left and right driver circuits through the memory matrix, so the pitch of the word line driver circuits should be twice the pitch of the memory cells. This makes it possible to reduce the word line spacing beyond the limit imposed by the word line driver circuit pitch. Furthermore, since memory cells can be arranged at all intersections between word lines and bit lines, high integration of memory cells is possible. Also, since the word line does not pass over the word decoder circuit or word line driver circuit,
It can be configured with an easy slam design.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

The figure shows its configuration. First and second word decoder circuits 101.1 are disposed on both sides of a semiconductor substrate constituting a memory device.
02, and first and second word line driver circuits 20 are formed inside the decoder circuits 101 and 102, respectively.
1°202 is formed. A memory matrix 3θ is connected between the word line driver circuits 201 and 202.
form. That is, word decoder circuit 101,1
02 and word line driver circuits 201 and 202 are now formed along the bit line 4Q of the memory matrix 30, and each word line driver circuit 201, 202 is formed along the bit line 4Q of the memory matrix 30.
The word line 50 corresponding to the output of
It is configured to run above 0.

That is, two word lines are arranged within the driver circuit pitch that generates one word line output, and the pitch of the word decoder circuits 101 and 102 and the word line driver circuits 201 and 202 is as follows. The pitch of the memory cells 60, ie, twice the pitch of the word lines 50, can be made, and the word line spacing can be reduced.

Further, left and right first and second driver circuits 201.
202, word lines 50 each of alternating different signals.
runs on the memory matrix 30, the memory cells 60 can be placed at all intersections of the word lines 50 and the bit lines 40, and the memory cells 60 can be highly integrated.

Also, word decoder circuits 101, 102 and word line driver circuits 201, 20;! Toga Memory Matrix 3
0 on the left and right, each word line 50
does not pass over the decoder circuits 101 and 102 and the word line driver circuits 201 and 202, simplifying the /4' tan design.

〔Effect of the invention〕

As described above, according to the present invention, two sets of word decoder circuits and word line driver circuits are arranged on the left and right sides with the memory matrix in between, which solves the problem of high integration caused by the word line driver circuits and facilitates the notan design. A large-capacity semiconductor memory device can be realized by using this method.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention. 101.102...First and second word decoder circuits, 201,202...First and second word line driver circuits, 30...Memory matrix, 40.
...Bit line, 50...Word line, 60...Memory cell.

Claims (1)

[Claims] A memory matrix configured by arranging a large number of parallel word lines and a large number of bit lines set to intersect with the word lines; It is equipped with first and second word line driver circuits arranged and formed on both sides, and word decoder circuits formed respectively attached to the first and second driver circuits, and the plurality of word lines are arranged alternately. 1. A semiconductor memory device, wherein the semiconductor memory device is connected to first and second word line driver circuits.