JPS6273492A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS6273492A JPS6273492A JP60213948A JP21394885A JPS6273492A JP S6273492 A JPS6273492 A JP S6273492A JP 60213948 A JP60213948 A JP 60213948A JP 21394885 A JP21394885 A JP 21394885A JP S6273492 A JPS6273492 A JP S6273492A
- Authority
- JP
- Japan
- Prior art keywords
- inverse
- digit
- digit lines
- digit line
- sense amplifiers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発8Aは半導体メモリ装ftK関し、特にダイナミッ
クRAMのセンスアンプの配置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention 8A relates to a semiconductor memory device ftK, and particularly relates to the arrangement of a sense amplifier of a dynamic RAM.
従来、第2図に示すように、メモリセルに接続するディ
ジット線Dl−D1〜D3・D3 の列の一方の端にの
みセンスアンプ81〜S3を配し、この−センスアンプ
S1に2本のティジット線D1・Dlを接続し、また、
他のセンスアンプ及びディジット綴金てにおいても同様
な構成となっていた。Conventionally, as shown in FIG. 2, sense amplifiers 81 to S3 are arranged only at one end of a row of digit lines Dl-D1 to D3 and D3 connected to memory cells, and two sense amplifiers are connected to this sense amplifier S1. Connect the Tigit wires D1 and Dl, and
Other sense amplifiers and digitizers had similar configurations.
上述した従来の半導体メモリ装置において、高集積化の
方間として、メモリセルサイズの縮小があり、七扛とと
もに、ディジット線間の間隔もちいさくなる。よって、
センスアンプの列方向に占める割合も小さくする必要か
める。しかし、センスアンフ全構成するトランジスタを
形成−jるノIC必要な大きさなどの制限によって、セ
ンスアンプの列方向の縮小には限界があり、これがメモ
リセルサイズと同じディジット線間の間隔よりも大きく
なると、メモリセルサイズがいくらちいさくてもセンス
アンプの列方向の大きさでディジット線間の間隔が決定
さn1メモリセルサイズの縮小が進んでも、チップサイ
ズは小さくならないなどの欠点かめる。In the conventional semiconductor memory device described above, the memory cell size is reduced as a means of achieving higher integration, and the spacing between the digit lines becomes smaller as well. Therefore,
It is also necessary to reduce the proportion of the sense amplifiers in the column direction. However, there is a limit to the reduction of the sense amplifier in the column direction due to restrictions such as the size of the IC required to form the transistors that make up the entire sense amplifier. Then, no matter how small the memory cell size is, the space between digit lines is determined by the size of the sense amplifier in the column direction, and even if the size of the n1 memory cell is reduced, the chip size will not be reduced.
本発明はディジット線列の両端に各々1列のセンスアン
プを配し、一方のセンスアンプ列のみに接続するディジ
ット線をこのディジット線列の奇数番目(ま九は、偶数
番目)に配し、他方のセンスアンプ列のみVC接続する
ディジット線をこのディジット線列の偶数番目(または
、奇数番目)に配している。The present invention arranges one row of sense amplifiers at each end of a digit line string, and arranges a digit line connected only to one sense amplifier string at an odd number (even number) of this digit line string, Digit lines to which only the other sense amplifier column is connected to VC are arranged at even-numbered (or odd-numbered) positions in this digit line column.
仄に、本発明について図面全参照して説明する。 The present invention will be briefly described with reference to all the drawings.
第1図は本発明の一実施例でめる。ディジット線DI、
DI〜D6.D6列の一方の端にセンスアンプ81〜8
3i配し、このセンスアンプ81,82゜S3 の各々
にディジット線D1・DI、D2・D2 、 D3・D
3 の各々2本を接続し、te、ディジット線DI、
DI〜D6.D6列の他方の端にセンスアンプ84〜S
6を配し、このセンスアンプ84,85゜S6の各々に
ディジット線D4・D4、D5・D5、D6・D6の各
々2本を接続する。FIG. 1 shows one embodiment of the present invention. digit line DI,
DI~D6. Sense amplifiers 81 to 8 are installed at one end of the D6 column.
The sense amplifiers 81 and 82°S3 each have digit lines D1/DI, D2/D2, and D3/D.
Connect two of each of 3, te, digit line DI,
DI~D6. Sense amplifiers 84 to S are installed at the other end of the D6 column.
6, and two digit lines D4, D4, D5, D5, and D6, D6 are connected to each of the sense amplifiers 84 and 85°S6.
この時、ディジット線DI!DI、D2・D2.D3・
D3をディジット線列の上方向から奇数番目に配し、デ
ィジット線D4・D4.D5・D5.D6・D6 t−
偶数番目に配している。こn以外のディジット線も同様
とする。At this time, digit line DI! DI, D2・D2. D3・
D3 is arranged at an odd number from the top of the digit line array, and digit lines D4, D4 . D5・D5. D6・D6 t-
Arranged in even numbers. The same applies to digit lines other than n.
以上説明したように本発明は、ディジット線の両端にセ
ンスアンプを配し、各ディジット線は1本ごとにディジ
ット線の両端各々Vc1列あるセンスアンプの片側の列
のセンスアンプに交互に接続することにより、ディジッ
ト線の片側にのみセンス7ンプが存在するときのセンス
アンブト同一ノものを使用して、このディジット線の間
隔を2分の1にすることができる効果かめる。As explained above, in the present invention, sense amplifiers are arranged at both ends of a digit line, and each digit line is alternately connected to sense amplifiers in one column of sense amplifiers, which have one column of Vc at each end of the digit line. As a result, when a sense amplifier is present on only one side of a digit line, the same sense amplifier can be used to reduce the interval between the digit lines by half.
第1図は本発明の一実施例に係る半導体メモリ装置のセ
ル周辺部のブロック図、第2図は従来の一般的な半導体
メモリ装置のセル周辺部のブロック図である。
1・・・・・・行デコーダ、Dl・Dl〜D6・D6・
・・・・・ディジット線、Ml〜M12・・・・・・メ
モリセル、81〜s6・・・センスアンプ、Wl、W2
・・・・・・ ワード線。
代理人 弁理士 内 原 晋 ゛4・、二ノ′
茅 l 圀FIG. 1 is a block diagram of a cell peripheral portion of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a cell peripheral portion of a conventional general semiconductor memory device. 1... Row decoder, Dl・Dl~D6・D6・
... Digit line, Ml to M12 ... Memory cell, 81 to s6 ... Sense amplifier, Wl, W2
・・・・・・ Word line. Agent Patent Attorney Susumu Uchihara ゛4., Nino' Kaya
Claims (1)
、前記一方のセンスアンプ列のみに接続するディジット
線を前記ディジット線列の奇数番目(または、偶数番目
)に配し、上記他方のセンスアンプ列のみに接続するデ
ィジット線を前記ディジット線列の偶数番目(または、
奇数番目)に配したことを特徴とする半導体メモリ装置
。One row of sense amplifiers is placed at each end of the digit line string, digit lines connected only to one of the sense amplifier strings are arranged at odd numbered (or even numbered) rows of the digit line string, and the other sense amplifier Connect digit lines that connect only to columns to even-numbered digit lines (or
A semiconductor memory device characterized in that the semiconductor memory device is arranged in an odd numbered position.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60213948A JPS6273492A (en) | 1985-09-26 | 1985-09-26 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60213948A JPS6273492A (en) | 1985-09-26 | 1985-09-26 | Semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6273492A true JPS6273492A (en) | 1987-04-04 |
Family
ID=16647699
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60213948A Pending JPS6273492A (en) | 1985-09-26 | 1985-09-26 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6273492A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5272665A (en) * | 1991-06-25 | 1993-12-21 | Oki Electric Industry Co., Ltd. | Semiconductor memory with improved sense amplifier layout |
KR100510463B1 (en) * | 1998-04-20 | 2005-10-24 | 삼성전자주식회사 | Semiconductor memory device having folded-bit line |
JP2010003464A (en) * | 2008-06-18 | 2010-01-07 | Sakaguchi Dennetsu Kk | Tape-shaped heater, and manufacturing method thereof |
JP2013079483A (en) * | 2008-05-28 | 2013-05-02 | Silveray Co Ltd | Electrically conductive pad and manufacturing method thereof |
-
1985
- 1985-09-26 JP JP60213948A patent/JPS6273492A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5272665A (en) * | 1991-06-25 | 1993-12-21 | Oki Electric Industry Co., Ltd. | Semiconductor memory with improved sense amplifier layout |
KR100510463B1 (en) * | 1998-04-20 | 2005-10-24 | 삼성전자주식회사 | Semiconductor memory device having folded-bit line |
JP2013079483A (en) * | 2008-05-28 | 2013-05-02 | Silveray Co Ltd | Electrically conductive pad and manufacturing method thereof |
JP2010003464A (en) * | 2008-06-18 | 2010-01-07 | Sakaguchi Dennetsu Kk | Tape-shaped heater, and manufacturing method thereof |
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