JPS6273492A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the space to a half between digit lines by providing a sense amplifier at both ends of the digit line and connecting each digit line alternately to the sense amplifier at one side row of the sense amplifier provided at both ends of every digit line. CONSTITUTION:Sense amplifiers S1-S3 are provided at one side end of rows D1, the inverse of D1-D6 and the inverse of D6 of the digit lines, and to each of the sense amplifiers S1, S2 and S3, each two digit lines D1/the inverse of D1, D2/the inverse of D2 and D3/the inverse of D3 is connected, and also, to the other end of the digit line rows D1, the inverse of D1-D6 and the inverse of D6, sense amplifiers S4-S6 are provided, and to each of the sense amplifiers S4, S5 and S6, each two digit lines D4/the inverse of D4, D5/the inverse of D5 and D6/the inverse of D6 are connected. At such a time, the digit lines D1/the inverse of D1, D2/the inverse of D2 and D3/the inverse of D3 are provided at the odd number of the digit line row from its upper direction and the digit lines D4/the inverse of D4, D5/the inverse of D5 and D6/the inverse of D6 are provided at the even number of the row. Another digit lines are arranged in the same manner.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention 8A relates to a semiconductor memory device ftK, and particularly relates to the arrangement of a sense amplifier of a dynamic RAM.

[Conventional technology]

Conventionally, as shown in FIG. 2, sense amplifiers 81 to S3 are arranged only at one end of a row of digit lines Dl-D1 to D3 and D3 connected to memory cells, and two sense amplifiers are connected to this sense amplifier S1. Connect the Tigit wires D1 and Dl, and
Other sense amplifiers and digitizers had similar configurations.

[Problem that the invention seeks to solve]

In the conventional semiconductor memory device described above, the memory cell size is reduced as a means of achieving higher integration, and the spacing between the digit lines becomes smaller as well. Therefore,
It is also necessary to reduce the proportion of the sense amplifiers in the column direction. However, there is a limit to the reduction of the sense amplifier in the column direction due to restrictions such as the size of the IC required to form the transistors that make up the entire sense amplifier. Then, no matter how small the memory cell size is, the space between digit lines is determined by the size of the sense amplifier in the column direction, and even if the size of the n1 memory cell is reduced, the chip size will not be reduced.

[Means for solving problems]

The present invention arranges one row of sense amplifiers at each end of a digit line string, and arranges a digit line connected only to one sense amplifier string at an odd number (even number) of this digit line string, Digit lines to which only the other sense amplifier column is connected to VC are arranged at even-numbered (or odd-numbered) positions in this digit line column.

〔Example〕

The present invention will be briefly described with reference to all the drawings.

FIG. 1 shows one embodiment of the present invention. digit line DI,
DI~D6. Sense amplifiers 81 to 8 are installed at one end of the D6 column.
The sense amplifiers 81 and 82°S3 each have digit lines D1/DI, D2/D2, and D3/D.
Connect two of each of 3, te, digit line DI,
DI~D6. Sense amplifiers 84 to S are installed at the other end of the D6 column.
6, and two digit lines D4, D4, D5, D5, and D6, D6 are connected to each of the sense amplifiers 84 and 85°S6.

At this time, digit line DI! DI, D2・D2. D3・
D3 is arranged at an odd number from the top of the digit line array, and digit lines D4, D4 . D5・D5. D6・D6 t-
Arranged in even numbers. The same applies to digit lines other than n.

〔Effect of the invention〕

As explained above, in the present invention, sense amplifiers are arranged at both ends of a digit line, and each digit line is alternately connected to sense amplifiers in one column of sense amplifiers, which have one column of Vc at each end of the digit line. As a result, when a sense amplifier is present on only one side of a digit line, the same sense amplifier can be used to reduce the interval between the digit lines by half.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a cell peripheral portion of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a cell peripheral portion of a conventional general semiconductor memory device. 1... Row decoder, Dl・Dl~D6・D6・
... Digit line, Ml to M12 ... Memory cell, 81 to s6 ... Sense amplifier, Wl, W2
・・・・・・ Word line. Agent Patent Attorney Susumu Uchihara ゛4., Nino' Kaya

Claims (1)

[Claims] One row of sense amplifiers is placed at each end of the digit line string, digit lines connected only to one of the sense amplifier strings are arranged at odd numbered (or even numbered) rows of the digit line string, and the other sense amplifier Connect digit lines that connect only to columns to even-numbered digit lines (or
A semiconductor memory device characterized in that the semiconductor memory device is arranged in an odd numbered position.