JPH0432091A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent an increase of a time difference generated at the time of ascent and descent of a word line by placing the same row decoder on both ends of the word line, respectively, and selecting the word line by driving simultaneously the row decoder circuits. CONSTITUTION:The same row decoders 5a, 5b are placed on both ends of a word line WL. In such a state, in the case a certain word line is selected, the same row address is supplied from an address buffer 3 and two sets of row decoders 5a, 5b are driven simultaneously. Accordingly, the capacity for allowing the word line WL to ascend or descend becomes two folds, comparing with a conventional one, and uniform driving can be executed extending overall length of the word line WL. In such a way, a time difference generated at the time of ascent and descent of the word line in the part being near the row decoder and in the part being distant from the row decoder on one piece of word line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a row decoder related to word line selection.

[Prior Art] FIG. 5 shows a block diagram of a conventionally used semiconductor memory device.

Generally, this type of semiconductor memory device consists of a memory cell array 1 arranged in rows and columns. In this memory cell, the presence or absence of accumulated charge indicates 1-bit data. In order to read data stored in a certain memory cell or write data to a certain memory cell, a memory cell must be selected from the memory cell array 1. The operation for selecting a memory cell will be described next. First, the row address of the selected memory cell is applied to the address pins AO to Ax, and then a row address strobe (hereinafter referred to as KK) signal is activated. When the 1 signal is activated at (3), the row address of the selected memory cell is latched into the address buffer 3 by the signal generated from the 3-clock generating circuit 2 at (π). Next, the column address of the selected memory cell is applied to the address bin AO-Ax, and then the column address strobe (hereinafter referred to as ff) is activated. When the nτ signal is activated, the column address of the memory cell to be selected is latched into the address buffer 3 by a signal generated from the third clock generation circuit 4. In this way, the row and column addresses applied to the address pins AO-Ax are decoded by the row decoder circuit 5 and column decoder circuit 6 through three address buffers. Then, one memory cell determined by one word line WL selected by row decoder circuit 5 and a digit line pair selected by column decoder circuit 6 was selected.

[Problems to be Solved by the Invention] In the conventional semiconductor memory device described above, the word line WL is selected by the row decoder 5 arranged at one end of the word line WL, as shown in FIG. Therefore, in the future, if the parasitic capacitance attached to a word line increases as semiconductor memory devices become more highly integrated, the word line will rise at the part near the row decoder and the part far from the row decoder on one word line, and There was a problem in that the time difference that occurs during descent increases.

[Means for Solving the Problems] The semiconductor memory device of the present invention is characterized in that identical row decoder circuits are arranged at both ends of a word line, and a word line is selected by driving these row decoder circuits all at once. shall be.

Further, the semiconductor memory device of the present invention is characterized in that a plurality of identical row decoder circuits are arranged on a word line, and a word line is selected by driving these row decoder circuits all at once.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram showing the arrangement of row decoders and word lines. Note that explanations that overlap with those of the conventional example will be omitted.

In this embodiment, row decoders 5a and 5b are arranged at both ends of word line WL. The two row decoders 5a and 5b arranged at both ends of the word line WL are the same, and when a certain word line is selected, the address buffer 3
The same row address is supplied from the row decoder 5a.
, 5b are both driven simultaneously. Therefore, word line W
The ability to boost or drop L is doubled compared to the conventional technology, and uniform driving can be performed over the entire length of the word line WL.

FIG. 3 is a block diagram of another embodiment of the present invention, and FIG. 4 is a block diagram showing the arrangement of word lines and row decoders. In this embodiment, the memory cell array is divided into two parts 1a and 1b, and a row decoder 5a is provided at each end of the word line WL.
, 5b are provided, and a row decoder 5c is also arranged at a half position on the word line WL. That is, three row decoders 5a, 5b, and 5c are arranged on one word line WL. These three row decoders 5a.

5b and 5c are all the same, and a certain word line W
When L is selected, these three row decoders are driven simultaneously.

Note that there is no limit to the number of row decoders placed on one word line, but when a certain word line is selected, all row decoders placed on this word line may be driven at the same time. .

[Effects of the Invention] As explained above, the present invention arranges row decoders at both ends of a word line or at a plurality of parts on the word line, and when a certain word line is selected, all of these row decoders are disposed at the same time. Even if semiconductor memory devices become more highly integrated and the parasitic capacitance attached to word lines increases in the future, by driving This has the effect of reducing the time difference that occurs when the line rises and falls.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram showing the arrangement of word lines and row decoders, and FIG.
The figure is a block diagram of another embodiment of the present invention, FIG. 4 is a block diagram showing the arrangement of word lines and row decoders, and FIG.
The figure is a block diagram of a conventional example, and FIG. 6 is a block diagram showing the arrangement of word lines and row decoders. SA...φ......Sense amplifier, MC...
・・・・・・・・・Memory cell, 1, la, lb...
...Memory cell array, 5+5 at 5
b, 5 C"・"'Row decoder, 6.6a, 6
b...Column decoder, WL...
...Word line. Patent applicant: NEC Corporation

Claims (2)

[Claims] (1) A semiconductor memory device characterized in that identical row decoder circuits are arranged at both ends of a word line, and a word line is selected by driving these row decoder circuits all at once. (2) A semiconductor memory device characterized in that a plurality of identical row decoder circuits are arranged on a word line, and a word line is selected by driving these row decoder circuits all at once.