JPH04285796A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To store a large capacity chip information without significantly increasing the required area of a semiconductor storage device especially the storage device which has, in addition to an ordinary storage section, an excess storage region within a chip to store an information such as semiconductor chip information. CONSTITUTION:Right next to a cell array 10, which is used to store the data of a semiconductor storage device, a cell group, which has the same kind of cells of the above mentioned cell array, is provided and a storage region 20, which is accessible by a word decoder 12 of the cell array and/or a column decoder 14 through the use of a special operation, is provided and a chip information is written into the cells of the storage region and the data are read out by the special operation. Thus, a large capacity chip information is stored without increasing the required area.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a semiconductor memory device, in particular,
The present invention relates to a memory device that includes, in addition to a normal memory portion, an extra memory area within the chip for storing information such as information related to a semiconductor chip. In an EPROM or the like, information regarding the silicon signature (information regarding the semiconductor chip) is stored in a circuit on the chip, and this information is read out and used when necessary.

0002

2. Description of the Related Art FIG. 4 shows a conventional example. 10 is EPROM
12 is a word decoder that selects the word line WL; 14 is a column decoder (including a sense amplifier) that selects the bit line BL; 16 is a peripheral circuit that receives an address ADD and a control signal SC from the outside;
It exchanges data with the input/output device I/O. For example, when writing, supply /WE etc. as SC, the write address as ADD, and the write data as I/O to the peripheral circuit 16, which causes the word decoder 12 to select the word line WL, and the column decoder 14 to select the bit line. BL
are selected, and the write data is written into the memory cells MC at the intersections thereof. The write data transmission path is I.
/O, 16, 14, BL, MC. In addition, when reading, the inversion of /WE is given as SC and the read address is given as ADD, which causes the word decoder and column decoder to select the word line and bit line, and the data stored in the memory cell MC at the intersection of these is sent to BL. ,14,16,
Extract via I/O route.

In such a memory device, chip information is written in a memory means 18 separate from the cell array 10, etc.
Chip information CI is read out by a special operation such as applying a high voltage to a certain terminal pin. The chip information CI is used, for example, in testing this storage device. In this case, a storage device testing device is connected to the I/O, and the CI is 18, 16, I/O.
It is taken into the test equipment via the route O and used for determining the test method. Specifically, the storage means 18 is a mask ROM.
This is created at the manufacturing stage of the storage device and data is written therein.

0004

[Problems to be Solved by the Invention] Currently, chip information is about several bytes, and does not have a large capacity. If it's a few bytes,
Even if there are 8 data lines and 1 byte, several sets of 8 1-bit storage elements are sufficient, and these can be connected to the data lines by a selector and read out in byte units. If the chip information has a small capacity as described above, it is sufficient to store it in a circuit, but it is expected that the amount of such information will increase in the future. If the size increases to hundreds of bytes or kilobytes,
Storing these as part of the peripheral circuit increases the required area, which may lead to a decrease in the degree of integration. The present invention improves these points without significantly increasing the required area.
The purpose is to be able to store large amounts of chip information.

[0005]

SUMMARY OF THE INVENTION As shown in FIG. 1, in the present invention, a chip information storage area 20 is provided adjacent to a cell array 10 for normal data storage. The memory cells in storage area 20 are the same as those in cell array 10, are connected to the same bit line BL, and are therefore selected by column decoder 14. In FIG. 1(a), such memory cells are provided for one word line, and in FIG. 1(b), such memory cells are provided for a plurality of word lines.

[0006]

[Operation] With the configuration shown in FIG. 1, a large capacity chip information storage area can be easily created without requiring a large area. For example, the cell array 10 is 1024×1024
Assuming that =1048576 bits, in (a) it is one word line, so 1024 bits can be easily obtained, and in (b) if it is four word lines, a storage area of 4096 bits, which is four times that amount, can easily be obtained.

The column decoder necessary to select these memory cells can be the column decoder 14 of the normal cell array 10. In (b), word line selection can also be performed using the word decoder 12. In (a), the word line WLa of the storage area 20 is not selected by the word decoder, but it can be brought into a selected state (H level) by a special operation such as applying a high voltage to a certain terminal pin. Also (b)
Then, the word decoder 12 selects the word line WL of the storage area 20.
A to WLn are selected, but this can also be done by special operation. For example, when a certain signal is input, the word decoder 12 selects the memory area 2 instead of the word line of the cell array 10.
The zero word line may be selected according to the input address bits. For the certain signal mentioned above, the address of the cell array can be set to A0 to A16 and the next A17 bit. The memory cells in the storage area 20 do not have to be exactly the same as the memory cells in the cell array 10, as long as they can be selected by the same word line and bit line. Of course, it needs to be non-volatile.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS To further explain the memory device shown in FIG. 1, this memory device has eight data lines in this example, and writing/reading to/from the cell array 10 is performed in units of bytes. In line with this, writing/reading of the storage area 20 is also performed in byte units, and the selected cell group can be changed by changing the column address in FIG. 1(a), and in addition to this by changing the column address in FIG. This is done by changing the .

One method of special operation for accessing the storage area 20 is to apply a high voltage to a certain terminal pin, and in FIG. 2(a), an address terminal pin is used as the terminal pin. That is, the storage device of this example has a VSS terminal, a VCC terminal, a /CE terminal, and 16-bit address terminals A0 to A0.
A16 and each terminal I/O0 for 8-bit data input/output
7 to 7, and when reading chip information, a high voltage is applied to the A16 terminal of these to select the storage area 20. In addition, in FIG. 2(b), a special terminal /C for the storage area 20 is
Normally, H level is applied to this terminal, but when accessing the storage area 20, L level is applied to this terminal.

FIG. 3 shows another embodiment. In FIG. 1, the storage area 20 for chip information is provided in the word line direction, but in FIG.
In (a), it is provided in the bit line direction. The capacity of the storage area 20 is assumed to be one word line or multiple word lines. Assuming that the cell array 10 is 1024×1024 bits, the capacity of the storage area 20 is 1024 bits for one word line, and multiple times that amount for multiple word lines. Cell selection in the storage area 20 is performed by changing the word address in the former case, and by changing the word address and column address in the latter case. The cells of storage area 20 may not be the same as the cells of cell array 10, and in this case may be larger than the cells of cell array 10. For example, the memory cells of the cell array 10 are SR
Such cases include AM or DRAM cells, memory cells in the storage area 20 are EPROM cells, and the like. If they are large, it is not easy to arrange them at the same pitch. FIG. 3B deals with such a case; in the storage area 20, only one out of every two word lines of the cell array 10 is connected to the storage area 20.
It does not extend to 0. In this way, the space in the storage area 20 becomes larger, so that large-sized memory cells can be accommodated sufficiently. In this case, the word address for accessing the storage area 20 is smaller than that for accessing the cell array 10.
For example, the lowest word address bit may be removed.

[0011]

As explained above, according to the present invention, a large capacity storage area for storing chip information can be easily secured. When storing a large amount of information, it is advantageous to arrange memory cells in a matrix, but in this case a decoder is required to select the vertical/horizontal lines (word/bit lines) of the matrix. Since these utilize the existing memory cell array, the required area can also be reduced in this respect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is an explanatory diagram of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of another embodiment of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

10 Cell array 12 Word decoder 14 Column decoder 16 Peripheral circuit 20 Storage area WL word line BL bit line

Claims (4)

[Claims] 1. A semiconductor memory device equipped with chip information, which has a group of cells of the same type as the cells of the cell array adjacent to a cell array (10) for data storage, and which has a group of cells of the same type as the cells of the cell array by performing a special operation. Word decoder (12)
A semiconductor memory device characterized in that a storage area (20) accessible by a column decoder (14) is provided, chip information is written in the cells of the storage area, and it is made readable by a special operation. . 2. The semiconductor memory device according to claim 1, wherein the storage area (20) extends in the word line direction of the cell array and has memory cells for one or more word lines of the cell array. 3. The semiconductor memory device according to claim 1, wherein the storage area (20) extends in the bit line direction of the cell array and has memory cells for one or more bit lines of the cell array. 4. A cell array according to claim 1, wherein one or more word lines of the cell array extend to the memory area (20) every other word line, and the cell density of the memory area is a plurality of the cell density of the cell array. 3. The semiconductor storage device according to 3.