JPH02246090A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To decrease a chip area by using a selective gate means which is opened/closed by means of a selector, and sharing a data latch. CONSTITUTION:A laterally wired layer is made into a second data bus, a data bus l12 is connected to a data bus DB2 which is extended in parallel with a left sense amplifier array, since eight data buses DB2 exist, eight data buses l12 are prepared, the data bus l13 is connected to a data bus DB3 extended in parallel with a right sense amplifier array, and the eight data buses DB3 exist in the same way. They are connected through selective gates 31 and 32 opened/closed by a selector 35 to a common data latch DL. Since the right and left memory cell blocks are not simultaneously selected, the data latch DL can be shared, and the read data fetched to the data latch can be outputted to the outside. Thus the chip area can be decreased.

Description

[Detailed Description of the Invention] [Summary of the Invention] An object of the present invention is to further reduce the required chip area by performing efficient wiring with regard to wiring on a semiconductor memory device, particularly its cells/sense amplifiers, and to provide a plurality of words. In a semiconductor memory device that includes a line, a bit line, a sense amplifier provided for each bit line, and a data bus that extends parallel to a column of these sense amplifiers and takes out the bit line potential amplified by the sense amplifier to the outside, the data A wiring layer is provided that is orthogonal to the bus and passes over the memory cell or over the memory cell and sense amplifier, and this wiring layer is used not only as a column selection line but also as a second data bus line, a sense amplifier drive signal line, etc. The signal line and power supply voltage wiring are configured to include one or more of the signal line and the power supply voltage wiring.

[Industrial application field]

The present invention relates to a semiconductor memory device, particularly to wiring on a cell/sense amplifier thereof.

In recent semiconductor memory devices, as the bit capacity increases, it is desired to reduce the area required for each part. Although miniaturization is effective in reducing the required area, efficient wiring is also important.

(Prior art) Semiconductor storage devices use word lines, bit lines, data buses,
A large number of wiring such as sense amplifier drive lines, column selection lines, power supply lines, etc. are used. The larger the capacity of the memory becomes, the larger the number of these wirings becomes, and the wiring area is multilayered to reduce the wiring area.

Figure 5 shows a conventional example.WL running vertically is a word line, BL running horizontally, BL is a bit line, and there are many of these, and a memory is placed at the intersection of each word line and bit line. A cell MC is provided. A pair of bit lines BL, B
A block M includes L, its memory cell MC, sense amplifier SA, etc. Indicated by s M61*..., a large number of these are arranged vertically (M,...

Mol, .
In the figure, Mo, and Ml. Only the following are shown in detail, and the rest are omitted. Data buses DBt, DB' run parallel to the columns of sense amplifiers SA arranged in the vertical direction, and column gates G z ,
The bit line BL, BL is connected to the data bus DB by Gs,
DB, to the corresponding pair of DBs. This memory is a 4-bit simultaneous read type, for example Mo. The four blocks BL and BL of M and 3 are connected to corresponding lines of eight data buses DB2 through column gates. The data read onto the data bus DB is latched into the data latch DL, passes through the gate G, and then passes through the eight data buses DB running in the horizontal direction.
It is taken out to the outside through.

Lines 1+ and lz running in the vertical direction are sense amplifier drive signal lines, it is connected to the power supply line VC and line through the gate G, and 2g is connected to the power supply line V and II through the gate G and the sense amplifier. Controls the operation/non-operation of. Game) G4
and Gs, Ga and G are cut gates, Q, and Q2 and Q, and Q4 are transistors for shorting (resetting) bit lines BL and BL', 2, and! , are signal lines for turning on/off the transistor, and lh and 1m are power supply wirings for shorting the bit line. The same applies to other blocks.

The X decoder 10 performs word line selection, and the Y decoder 2
0 is a bit line selection, in this example four pairs of bit lines are selected each, and DR is a gate driver.

The memory cells are on the left and right of the sense amplifier, but when selecting the memory cell on the left, use the cut gate on the right)G,,G
, the right side memory cell group is separated, and when selecting the right side memory cell, the left side memory cell group is separated using the left cut gate.

Generally, a bit line is composed of polycrystalline silicon formed on a substrate and a diffusion layer. The word line, together with the gate of the transistor of the memory cell, is made of polycrystalline silicon or metal (aluminum) wiring (the latter in this example). Further, the memory cell is formed of two layers of polysilicon considering a stacked cell. Therefore, the memory of this example has seven layers of wiring, including four layers of polysilicon, two layers of aluminum, and a diffusion layer. Data buses DB, DB, etc. running in the vertical direction and column selection lines IIs, Its, etc. running in the horizontal direction use the first and second layers of two-layer aluminum wiring, and column selection lines 1s, Ila, etc. left,
Blocks M, o and M on the right. The space is shared by other facilities to reduce the area required.

[Problem to be solved by the invention]

However, in the semiconductor memory device shown in FIG. 5, the data bus DB! parallel to the sense amplifier row! , DB, and the common data bus DB is provided not in the cell array/sense amplifier area but in the wiring area around it, so that the required area is not sufficiently reduced.

16 MDRA? Some large-capacity memories such as the 16-bit test mode have a 16-bit test mode, and in this case, the data bus has 16 bears. This means that if the wiring pitch is 3μm, the data bus width is 16X2X'3ζ100μm,
If the data bus DB extends along the cell array, the chip area will be consumed considerably.

In addition, the power supply VCC line and the v and s lines are extended in the horizontal direction, and power is supplied from these to the sense amplifier drive signal lines II and it which extend in the vertical direction via the transistors G1° and G.
For example, if we consider eliminating the delay in sense amplifier operation due to the wiring resistance of the power supply line, 113? In tDRAM, V
Both the CC line and the Vss line require a width of 100 to 150 um, which also causes an increase in chip area due to an increase in length in the sense amplifier column direction.

The present invention aims to improve these points, and aims to further reduce the required chip area by performing efficient wiring.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, a plurality of word lines WL, bit lines BL, BL, and each bit line BL.

Sense amplifiers SA provided in BL and data buses DBt and DB extending parallel to the rows of these sense amplifiers SA.
, the data bus DB□DB
, and passes over the memory cell or over the memory cell and sense amplifier 111+ l +! + 4
! +3 is provided, and these wiring layers are connected to the column selection line III.
In addition to the second data bus lines z, , j
! 13. Use either the sense amplifier drive signal line, other signal line, or power supply voltage line.

[Effect]

With this configuration, the required area can be further reduced. That is, the horizontal wiring layer L2+ j! If 13 is the second data bus, this corresponds to the common data bus DB in FIG. 5, but L! Since l1AI3 runs on the cell array and sense amplifier, it does not increase the chip area. Further, only one data latch DL needs to be provided for common use by the left and right blocks of cells that are not shared with the sense amplifier, thereby reducing the required area.

■Power supply for horizontal wiring layer. , ■1. When used as a line, it has a wide width, but because it passes over the cell array rather than through the wiring area, it is effective in reducing the chip area.

〔Example〕

Embodiments of the present invention are shown in FIGS. 2 and 3. As in all figures, parts that are the same as in other figures are given the same reference numerals.

FIG. 2 shows an example in which the horizontal wiring layer is used as the second data bus, the data bus lI! are connected to the data bus DB, which runs parallel to the row of sense amplifiers on the left, and in this example, there are eight DB, so i, I! There are also 8 pieces.

Data bus 21. are connected to the data bus DB, which runs parallel to the row of sense amplifiers on the right side, and similarly there are eight buses.

These are connected to a common data latch DL via selection gates 31 and 32 that are opened and closed by a selector 35. Since the left and right memory cell blocks are never selected at the same time, the data latch DL can be shared. The read data taken into this data latch is output to the outside via a path not shown.

Lateral wiring 23. is used for other signal lines. The horizontal signal line 2■ is connected to a Y decoder and used for column selection, and corresponds to the signal lines 1x and Ilm in FIG. This memory is also a 4-bit simultaneous selection type.

FIG. 3 shows an example of using a horizontal wiring layer as a sense amplifier drive signal line (more specifically, on the power supply V CCr Lm side), and shows a wide wiring layer j! 14s j! I'l is that, and the wiring layer 21th is connected to the power supply ■ via the gate Gll. A drive signal line that connects to the line and runs in the vertical direction of the sense amplifier SA! 2 through a through hole H. In addition, the wiring layer Lv is connected to the power supply ■ via Goo. In this example, these j'l & + z
,, are also connected to the vertically running drive signal line of the sense amplifier on the right side through a through hole, but this is '1&+L?
It is also possible to make a plurality of them and connect them separately.

By doing this, the upper and lower VCC lines and V
The ss lines can be omitted, and since they are wide, they are effective in reducing lff in the required area.

Although only two sense amplifier rows are shown in FIGS. 2 and 3, there will be many more sense amplifier rows in a large-capacity memory. FIG. 4 shows a 16M bit memory. In this case, 16 1M cell blocks are lined up as shown in the figure, and each cell block has 2
The configuration is such that there are two cell blocks at 512 with a sense amplifier row sandwiched between them.

In this case, in order to operate the sense amplifier row in divided manner,
In sense amplifier arrays that do not operate simultaneously, data latches can be shared by means of selection gates 31, 32 which are opened and closed by selector 35 in FIG.

Wiring layer j running horizontally, that is, in a direction perpendicular to the sense amplifier row!
ll+ '1! +... runs across these cell blocks to the required part.

〔Effect of the invention〕

As explained above, in the present invention, the wiring layer running on the cell array sense amplifier in the direction orthogonal to the sense amplifier row allows the connection of the second data bus line, sense amplifier drive signal line, other signal lines, and power supply voltage wiring. Since there are one or more, the chip area can be reduced compared to a case where these are provided in the wiring area. Further, the wiring layer is used as a second data bus,
Sharing data latches is also effective in saving area.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, and FIGS. 2 and 3 are diagrams showing the principle of the present invention. FIG. 4 is an explanatory diagram showing the second embodiment, FIG. 4 is an explanatory diagram of the layout of a cell/sense amplifier of a large capacity memory, and FIG. 5 is an explanatory diagram of a conventional example. In FIG. 1, WL is a word line, BL is a bit, LMC is a memory cell, SA is a sense amplifier, and DB! , DB, is the data bus, j! 13 is a wiring layer, and DL is a data latch.

Claims (1)

[Claims] 1. A plurality of word lines and bit lines, a sense amplifier provided for each bit line, and a line extending parallel to the rows of these sense amplifiers, and extracting the bit line potential amplified by the sense amplifier to the outside. In a semiconductor memory device equipped with a data bus, a wiring layer is provided which is orthogonal to the data bus and passes over memory cells or over memory cells and sense amplifiers, and the wiring layer is used not only as a column selection line but also as a second line. data bus line,
A semiconductor memory device comprising one or more of a sense amplifier drive signal line, another signal line, and a power supply voltage line.