JPS60246092A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the speed of a RAM and also to reduce the size of a chip by providing a gathering line of sense amplifiers consisting of a conduction layer equal to the signal lines forming a two-intersection point type dynamic RAM between said signal lines and connecting an end of the gathering line to a pull- out switch element provided outside a memory array. CONSTITUTION:Gathering lines PN consisting of aluminum layers of the same number as signals lines YS are provided among these lines YS. The common sources CS for sense amplifiers included into sense amplifier trains SA1-SA8 are connected every four pieces to the drain of each pull-out MOSFETQDT. As a result, the wiring length is shortened up to the sense amplifier at the remotest end. Further more the total sectional area is increased by the separate lines PN compared with a single unified line PN although the thickness of each line PN is reduced. As a result, the resistance of the line PN through which the common source CS of each sense amplifier is connected to the QDT is reduced. This improve the reading speed. In such a way, the divided lines PN are provided through the originally idle areas among lines YS. Thus the width (lateral in the figure) of a memory array M-ARY is reduced and therefore the chip size is also recued.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor integrated circuit technology and also to semiconductor storage devices, such as dynamic RAM (wiring method in Random Access Memo January). Concerning techniques that can be used effectively.

[Background Art] Conventionally, as a method for configuring a memory array in a dynamic RAM, a single intersection method (or an open wire) is used, in which a set of pin 1 lines connected to a sense amplifier are extended symmetrically on both sides of the sense amplifier.・Bit line method) and a 2' intersection method (or folded bit line method) in which a negative set of bit lines are extended parallel to each other on one side of the sense amplifier.

By the way, in a semiconductor memory, in order to select memory cells arranged in a matrix, word lines and bit lines (or data lines) are necessarily arranged so as to be orthogonal to each other. Therefore, if aluminum wiring is used for either the word line or the bit line, it becomes difficult to form the other signal line using the same aluminum wiring layer. Therefore, conventionally, in a 1-point-1 intersection type RAM, the word line arranged in the longitudinal direction of the memory array is formed of an aluminum layer, and the line to the first pin perpendicular to this is formed of a polysilicon layer. was being treated as

On the other hand, in the two-intersection type RAM, the bit line is generally formed of an aluminum layer, and the word line is formed of a polysilicon layer that is integrated with the gate electrode of the selection switch MO8FET that constitutes the memory cell. Moreover,
In this case, in order to reduce the resistance of the word line made of polysilicon, the word line was arranged along the short direction of the memory array (Nikkei Electronics).

August 30, 1982, No. 298. Page 162~
(See page 165).

On the other hand, in a dynamic RAM, for example, as shown in FIG. 1, MO8FE'I"Ql,
A latch type sense amplifier SA consisting of Q2 and a MOS FET QDT for extraction is used.
The sense amplifiers SA are arranged in the same direction as the word lines W in the same number as the bit line sets. Since these sense amplifiers SA are operated simultaneously when reading data,
The MOSFE TQDT for extraction is designed to be shared with each other.

Therefore, a very large current is passed through the MOS FET QDT for extraction, so the element size must be made very large compared to other MOSFETs. Therefore, the MOS for extraction
FETQDT is outside the memory array.

Moreover, the power supply pad Ps (second
It is preferable to install it on the side close to the

However, the M for extraction common to each sense amplifier
If the OS FET QDT is arranged outside the memory array, wiring must be formed to connect each sense amplifier SA in the memory array to the MOS FET QDT for extraction. Moreover, in this case, the MO3FETQ for extraction from each sense amplifier SA
Care must be taken to ensure that the wiring up to DT is not short-circuited with the word line W and bit lines BL, BI- arranged vertically and horizontally within the memory array.

Therefore, the present inventor proposed a two-intersection type dynamic RAM.
For example, a method as shown in FIG. 2 was developed as a method for arranging the wiring connecting each sense amplifier to the MOSFET for extraction.

That is, for example, as shown in the figure, eight memory pines h M
Memory array M-ARY divided into M+~MM8
At the center of of,
Form along the longitudinal direction. Then, common source lines CSL, ~csr-8 are connected to the signal line ys from this collective line PN for each memory mat MM, ~MM8.
It is formed of an aluminum layer different from that of the memory array, is extended, is connected to the collection line PN in 1 on the center side, and has one end of the collection line PN placed outside the memory array for extraction (7).
M OS' F E T Q D T (7) ”/
- contact with the base (diffusion layer).

However, with such a wiring system, there is no particular problem in a RAM with a relatively small storage capacity, but when it comes to RAMs with 256 bits or more than 1M bits, the resistance of the aluminum wiring cannot be ignored. Therefore, each sense amplifier SA in the memory array is connected to a common extraction MOS.
Common source line CS connected to FET Q DT
It has been found that the resistance of L1-C3L8 and the collection line PN slows down data reading. Moreover, the cross-sectional area (particularly the width) of the collective line PN through which a large current flows must be increased to some extent in order to lower the resistance value, which inconveniently increases the width of the memory array and increases the chip size. There is.

In FIG. 1, below Q p r Q is an MO8FET for precharging the sense amplifier SA, and MC is a memory cell.

[Objective of the Invention] The object of the present invention is to provide a sense amplifier common source line arrangement method that can improve read speed and reduce chip size when applied to, for example, a two-intersection type dynamic RAM. Our goal is to provide the following.

The above and other objects and novel features of the present invention will become clear from the description of this document and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, in the two-intersection type dynamic RAM, we focused on the fact that the signal lines that transmit the signals that operate the column switches are relatively open, and between these signal lines, we connect a collection of sense amplifier lines made of the same conductive layer. , and the sense amplifiers are brought into contact with the aggregate line at a position where they intersect with the sense amplifier rows arranged along the word line direction, and one end of the aggregate line is placed outside the memory array. By making the connection to the installed pull-out switch element, it is not necessary to arrange a thick collective line especially in the center of the memory array, reducing the chip size and dividing the common source line into multiple parts. By arranging them, the total cross-sectional area is increased and the wiring resistance is lowered, thereby achieving the above-mentioned purpose of increasing the data read speed by -1.

The present invention will be described in detail below along with examples.

[Example] FIG. 3 shows the present invention in a two-intersection dynamic type R,
A schematic configuration diagram of an embodiment when applied to AM is shown.

In this embodiment, although not particularly limited, the memory array M
-ARY is divided horizontally into two and vertically into four, and is constituted by eight memory mats MM to MM8.

Between memory mats MM and MM, between MM'3 and MM4, between MM6 and MM6, and between MM7 and MM, there is a common X decoder that decodes the X system address signal and a selection signal for this X decoder. By Memory Mat MMi
~A word line selection drive circuit X- consisting of a word driver that drives word lines W extending laterally within MM8.
A DEC is provided for each. The word line W is formed by a polysilicon layer integrated with the gate electrode of the MO'5FETQs in the memory cell MC, which consists of an information charge storage capacitor Cs and a selection switch MOSFETQs as shown in FIG. It is formed.

Further, in the center of each memory mat MM1 to MMa, two sense amplifiers SA having a circuit type as shown in FIG.
Sense amplifier arrays SAI to SA8 are arranged back-to-back in a line equal in number to the number of pairs of bit lines BL and BL.
However, each of them is provided. This sense amplifier row 5A
Bit lines BL, BL extend from I-8A8 along a direction perpendicular to the word line W (downward direction in the drawing). The bit lines BL, BL are formed of the first aluminum layer, although not particularly limited thereto.

One side (lower side in the drawing) of the memory array M-ARY is provided with a column switch M for each bit line BL and BLJ2 as shown in FIG. OS F F″＞T” Q y' r
Y that forms the selection signal φy for turning on Q'5;
A decoder Y-DEC is provided. And this Y
The selection signal φy is sent upward from the decoder Y-DEC into the memory array M-ARY to the column switch MO8.
A plurality of signal lines YS for transmitting signals to the FETs Q"/, Qy are extended in parallel with each other at appropriate intervals.

This signal YS crosses the bit lines BL and B main in the memory array, so the bit lines BL and
It is formed by a second aluminum layer different from the BL.

On the other hand, in this embodiment, the above Y of memory array M-ARY
On one side opposite to the decoder Y-DEC (upper side in the drawing),
MO8F E T Q D for extracting sense amplifier SA
T is provided. And this MOS for extraction
F E T Q o T to memory array M-ARY
Inward and downward, the common source C8 of the sense amplifier SA as shown in FIG.
Q: A plurality of aggregate lines PN are extended to connect to the drain of the DT. This set line PN is connected to each sense amplifier column SΔ1. ．． SA3. SA5. SA7 or SA
2. SA, 4. S.A.G.

They are each connected to a common source O8 in the sense amplifier SA at a position where they intersect with SA8.

Moreover, this set line PN is connected to the Y-decoder Y-DEC.
Since the interval between the signal lines YS extending upward from 9 is relatively wide, the signal lines YS are arranged parallel to each other between the signal lines 78. Therefore, the aggregate line PN is formed of the same second aluminum layer as the signal line YS, since there is no risk of it being short-circuited with the signal line YS.

In this way, in this embodiment, the collective line PN made of the same number of aluminum layers is arranged between line A8 YS, and the common source O8 of the sense amplifiers in each sense amplifier array SAI to SAB is M for pulling out 4 pieces each
It is connected to the drain of OSFETQoT. Therefore, as shown in Fig. 2, the common sources of the sense amplifiers are grouped together for each sense amplifier row using a common source ACSL, and then connected to the collective line PN for extraction. MO'5FET
Compared to the method of connecting to a QDT, the wiring length to the farthest sense amplifier is shorter. Moreover, rather than combining the aggregate lines PN into one, if they are divided corresponding to the bit lines as in the embodiment 1, the total cross-sectional area will be larger even though each aggregate line is thin. .

As a result, the resistance of the collective line connecting the common source O8 of each sense amplifier to the extracting MOS FET QDT is reduced, and the read speed is improved.

In addition, there is no need to arrange a thick aggregate line in the center of the memory array, and since the area between the signal lines 78 that was originally vacant is used to provide the divided aggregate lines PN, the memory array M -The width of the ARY (in the lateral direction in the drawing) can be narrowed, thereby reducing the chip size.

Note that with current aluminum two-layer wiring technology, the second aluminum layer is not brought into direct contact with the diffusion layer;
This is always done through the second aluminum layer. Therefore, in the above embodiment, the ends of the collective wires PN made of the second aluminum layer are connected to the drawing MOSFET Qo through the second aluminum layer.
, are connected to the drains of T.

Furthermore, in this embodiment, although not particularly limited, in each sense amplifier array SAI to SAB, common sources Bcsr, which are made of a first aluminum layer, are arranged along the arrangement direction (horizontal direction) of the sense amplifiers. 1~CS L (
3 are arranged respectively. The common source C8 of the sense amplifiers in each sense amplifier column is connected to this common source C3L.

As a result, each sense amplifier is also connected laterally, and for example, even if the connection between the common source and the collective line PN in a certain sense amplifier is uncertain, the connection between the common source and the collective line PN is , are connected to the aggregate line PN to which adjacent sense amplifiers are connected, and the charge of the common source is extracted. As a result, circuit reliability is improved and yield is improved.

However, this common source line csr-, ~C3L8
does not necessarily need to be provided and can be omitted. When common source lines csL1 to C3L8 are provided,
Since each collective line PN can be connected to the common source line C8 of the corresponding sense amplifier through the common source lines C8L, ~C3L8, the collective line PN made of the second aluminum layer can be connected to the common source line C8 of the sense amplifier. There is no particular need to provide a buffering aluminum layer (first layer) connected to the common source line cs.

In the above embodiment, the memory array is divided into eight mats, but the memory array can also be divided into eight or twelve mats.

[Effects] (1) In a two-intersection type dynamic RAM, a collective line of sense amplifiers made of the same conductive layer is arranged between the signal lines that transmit the selection signal that operates the column switch, and The sense amplifiers are brought into contact with the above aggregate line at a position where they intersect with the sense amplifier rows arranged along the direction, and one end of the aggregate line is connected to an extraction switch element arranged outside the memory array. As a result, there is no need to arrange thick collective lines in the center of the memory array, and the width of the memory array can be reduced by using the area between the vacant signal lines. This has the effect of reducing the chip size.

(2) In the two-intersection type dynamic type R, AM, a collection line of sense amplifiers made of the same conductive layer is arranged between the signal lines that convey the selection signal that operates the column switch, and The sense amplifiers are brought into contact with the collective line at a position where they intersect with the sense amplifier rows arranged along the direction.

In addition, one end of the collective wire is connected to the pull-out switch element arranged outside the memory array, so the total cross-sectional area of the common source wire can be reduced by dividing the common source wire into multiple parts and arranging them. This effect of increasing the size and reducing the interconnect resistance has the effect of increasing the read speed and increasing the memory speed.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the Examples described in L, and it is possible to make various changes without departing from the gist thereof. Not even. For example, in the embodiment described above, the bit lines and common source lines are formed from the first aluminum layer, and the aggregate lines are formed from the second aluminum layer, but the reverse relationship is also possible. . Further, in the embodiment described above, the common source line is formed of an aluminum layer, but the common sources of all sense amplifiers are connected to the MO8FET for extraction by a collective line. Therefore, even if the resistance value of the common source line is somewhat high, it does not significantly affect the read speed, so it is also possible to form the common source line with a polysilicon layer.

[Field of Application] In the above explanation, the invention made by the present inventor is mainly applied to the field of application which is the background of the invention, which is a two-intersection type dynamic RAM in which the sense amplifier is composed of an N-channel MOSFET. Although described above, the present invention is not limited thereto, and can also be used in a dynamic RAM having a CMO3 type sense amplifier.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the configuration of a sense amplifier in a two-intersection type dynamic RAM, and FIG.
FIG. 3 is an explanatory diagram showing an example of the configuration of a memory array in an intersection type dynamic RAM. FIG. 3 is an explanatory diagram showing an example of the configuration of a dynamic RAM to which the present invention is applied. SA...Sense amplifier, MC...Memory cell,
M-ARY...Memory array, MM, ~MM8 part
Memory mat, Y-DEC...X decoder, X-
D E C...X decoder, SAI~5A8-percent amplifier row, BL, BL...bit line, W...
...Word line, YS...Signal line, PN...Collection line, CS L, ~CS L a...Common source line, Ql)T...MO3FET for extraction, Qy,
Qy...Column switch, O8...Common source. Figure 1 Figure 2

Claims (1)

[Claims] 1. A plurality of signal lines disposed orthogonally to each other in a memory array access a memory cell located at the intersection of the signal lines, and a plurality of senses amplify the read signal. In a semiconductor memory device in which circuits are arranged in parallel with one signal line in a memory array, and a selection circuit for the other signal line is provided on one side of the memory array, A semiconductor memory device characterized in that a plurality of wires are formed in parallel with the wires, and the sense circuits in the memory array are connected to their common driving elements or circuits. 2. In a dynamic type semiconductor memory device that can be read and written at any time and has a two-cross point type memory array, each sense circuit in a sense circuit array arranged in parallel with a word line is Claim 1, characterized in that a wiring is formed between the bit lines to connect the common source in the sense circuit to an extraction switch element as a common driving element outside the memory array. The semiconductor storage device described in 1. 3. The semiconductor memory according to claim 2, wherein the wiring connecting the common source in the sense circuit 1 to the extraction switch element is formed of the same conductive layer as the bit line. Device. 4. A patent characterized in that the common sources in the sense circuit are arranged perpendicularly to the bit lines and interconnected by wiring formed of a conductive layer different from the bit lines. A semiconductor memory device according to claim 3. 5. The above-mentioned P1- wire is formed of a second layer of aluminum, and the wiring connecting the common source to the switching element for extraction is formed of a second layer of aluminum. The semiconductor memory device according to scope 4.