JPS61283120A - Ohmic electrode - Google Patents
Ohmic electrodeInfo
- Publication number
- JPS61283120A JPS61283120A JP12542585A JP12542585A JPS61283120A JP S61283120 A JPS61283120 A JP S61283120A JP 12542585 A JP12542585 A JP 12542585A JP 12542585 A JP12542585 A JP 12542585A JP S61283120 A JPS61283120 A JP S61283120A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- electrode
- emitter
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子のオーム性電極、特に高信頼のオー
ム性電極に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ohmic electrode for a semiconductor device, and particularly to a highly reliable ohmic electrode.
近年、InPやGaAS等の化合物半導体を用いた電子
素子が81を用いた素子以上に高速動作可能なことから
盛んに研究開発が行われている。ところでこれらの化合
物半導体では、一般に電子の移動度がホールのそれより
大きいことからnチャンネル電界効果トランジスタや、
npn型バイポーラトランジスタ等n型半導体の方
に高電流を注入する型の方がより高速動作させることが
できるが、上記の型の素子では高い信頼性を得る上で高
電流を注入するn型半導体に形成するオーム性電極が非
常に重要な位置を占める。従来からはAuGeを用いた
電極が知られていた(雑誌’ IEEE、 ELECT
RONDliVICE LE’rTEBjS ’ vo
l 、EDL−5No、6214(1984)参照)。In recent years, research and development has been actively conducted on electronic devices using compound semiconductors such as InP and GaAS because they can operate at higher speeds than devices using 81. By the way, in these compound semiconductors, the mobility of electrons is generally higher than that of holes, so they are used in n-channel field effect transistors,
Types that inject a high current into the n-type semiconductor, such as npn-type bipolar transistors, can operate at higher speeds, but in the above types of devices, in order to obtain high reliability, it is necessary to The ohmic electrode formed in this way occupies a very important position. Conventionally, electrodes using AuGe have been known (magazine' IEEE, ELECT
RONDliVICE LE'rTEBjS' vo
1, EDL-5 No. 6214 (1984)).
しかしながらこのようなん合金を用いた電極では麺が半
導体と反応を起こしやすく、特に高電流を注入する電極
として用いる場合には電極部での発熱が生じ、半導体と
電極との反応が促進され素子劣化の大きな要因となる欠
点を有していた。However, in electrodes using such alloys, the noodles tend to react with the semiconductor, and especially when used as an electrode for injecting high current, heat is generated at the electrode part, promoting the reaction between the semiconductor and the electrode, and deteriorating the element. It had a drawback that was a major factor.
本発明の目的は上記の欠点を除去し、高信頼かつ低接触
抵抗を有するオーム性電極を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks and provide an ohmic electrode having high reliability and low contact resistance.
本発明は少なくとも1X10c!IL以上のn型不純物
を含む半導体上に、少なくともTi及びptを順次積層
してなる金属膜を形成したことを特徴とするオーム性電
極である・
〔実施例〕
次に図面を参照して本実施例を詳細に説明する。The present invention uses at least 1X10c! This is an ohmic electrode characterized by forming a metal film formed by sequentially laminating at least Ti and PT on a semiconductor containing n-type impurities of IL or higher. Examples will be described in detail.
第1図は本発明を適用した一実施例の、クイポーラトラ
ンジスタの断面図である。このバイポーラトランジスタ
はFeドープの絶縁性InPよりなる基板1上に、層厚
が1μ翼でキャリア濃度がI X10 ”cm ”のn
型のIno、7=Gc 6.uAa 6.44P o、
ss よりなるコレクタコンタクト層2、層厚が0.3
μ惧でキャリア濃度がlXl0 cmのn型InPより
なるコレクタ層3、層厚が0.21Lmでキャリア濃度
がlX10cIrLのp型Ina4s(A+、xAa6
,44Pe、ssよりなるベース層4、層厚が0.24
ヤリア濃度が2×10CI!Lのn型InPよりなるエ
ミツタ層5、層厚が0.2μ倶でキャリア濃度がlX1
0cIrLのn型InPよシなるエミッタコンタクト層
6を有し、Ti及び汽を順次積層したエミッタ電極7、
ペース電極8、コレクタ電極9、麺よりなるワイヤボン
ディング用のカバー電極10及びS10.の保護膜11
より構成されている。FIG. 1 is a cross-sectional view of a quapolar transistor according to an embodiment of the present invention. This bipolar transistor has a layer thickness of 1μ on a substrate 1 made of Fe-doped insulating InP and a carrier concentration of I x 10 ``cm''.
Type Ino, 7=Gc 6. uAa 6.44P o,
Collector contact layer 2 consisting of ss, layer thickness 0.3
The collector layer 3 is made of n-type InP with a carrier concentration of 1X10 cm at 0.21 Lm, and the p-type InP (A+, xAa6
, 44Pe, ss, the layer thickness is 0.24
Yaria concentration is 2×10CI! The emitter layer 5 is made of L n-type InP, the layer thickness is 0.2μ, and the carrier concentration is lX1.
An emitter electrode 7 having an emitter contact layer 6 made of 0cIrL n-type InP, and having Ti and steam laminated in sequence;
A pace electrode 8, a collector electrode 9, a cover electrode 10 for wire bonding made of noodles, and S10. protective film 11
It is composed of
本発明の構造の素子を形成するには、基板l上にコレク
タコンタクト・!!”ia2’s’ コレクタ層3、ベ
ース層4、エミツタ層5、エミッタコンタクト層6が形
成されたものから、InPよりなる部分を塩酸及びリン
酸よりなるエツチング液でIno、?1Gao、5AI
5o、saP 6.Mよりなる部分を硫酸、過酸化水素
及び水よりなるエツチング液でそれぞれ選択的にメサエ
ッチングを行う0次にレジストを用いたリフトオフ法に
よシT1及びptを順次積層したエミッタ電極7、ベー
ス電極8、コレクタ電極9を形成し、さらにS10.を
G■により堆積しパターニングして保護膜11 ft形
成した後、カバー電極10をレジストによるリフトオフ
にて形成する。To form a device with the structure of the present invention, a collector contact ! ! ``ia2's'' From the layer where the collector layer 3, base layer 4, emitter layer 5, and emitter contact layer 6 are formed, the InP portion is etched using an etching solution of hydrochloric acid and phosphoric acid with Ino, ?1Gao, and 5AI.
5o, saP 6. An emitter electrode 7 and a base electrode in which T1 and PT are sequentially laminated by a lift-off method using a 0-order resist in which the portion consisting of M is selectively mesa-etched using an etching solution consisting of sulfuric acid, hydrogen peroxide, and water. 8. Form the collector electrode 9, and further perform S10. After depositing and patterning using G2 to form a protective film 11 ft thick, a cover electrode 10 is formed by lift-off using a resist.
以上実施例ではキャリア濃度1×10cIILとしたn
型半導体を電極コンタクト層として設けてその上にTi
及びptよりなる電極を形成しているため、従来のん合
金電極同程度のコンタクト抵抗にすることができるため
寄生抵抗の増大による素子の特性の劣化は全くない、そ
して、T1は半導体との反応に乏しく、またptはカバ
ー電極10の麺の半導体層への侵入を阻止しているため
、電極の劣化による信頼性の低下は大@←′仰えられる
。ま之、TI及びptよりなる電極はp型半導体に対し
てもオーム性電極となることが知られており、pen両
方のオーム性電極としての使用が可能となることから製
造工程も簡単になる。従って、従来に比べ特性を劣化さ
せることなく高信頼な素子の製造が可能となり・−遺工
程の簡略化ができることから製造歩留まりを向上させる
ことができる。In the above examples, the carrier concentration was set to 1×10cIIL.
A type semiconductor is provided as an electrode contact layer, and a Ti
Since the electrode is made of PT and PT, the contact resistance can be made comparable to that of conventional non-alloy electrodes, so there is no deterioration of the device characteristics due to an increase in parasitic resistance. Moreover, since PT prevents the noodles of the cover electrode 10 from penetrating into the semiconductor layer, it is said that reliability is greatly reduced due to deterioration of the electrode. It is known that electrodes made of TI and PT can also serve as ohmic electrodes for p-type semiconductors, and can be used as ohmic electrodes for both pens, which simplifies the manufacturing process. . Therefore, it is possible to manufacture a highly reliable element without deteriorating the characteristics compared to the conventional method, and the manufacturing yield can be improved because the post-process steps can be simplified.
なお、本発明はlXl0”m’以上のキャリア濃度を有
するn型伝導性の半導体であればいかなる混晶組成のも
のであってもよい、tfc電極となるTIはいかなる厚
さでもよく、ptは麺の侵入阻止可能な厚さであればい
かなる厚さでもよい、 。In addition, in the present invention, any mixed crystal composition may be used as long as it is an n-type conductive semiconductor having a carrier concentration of lXl0"m' or more, the TI serving as the TFC electrode may be of any thickness, and the PT may be of any thickness. It can be of any thickness as long as it can prevent noodles from entering.
以上説明したように、本発明によれば少なくともlX1
0cm以上のキャリア濃度を有するn型伝導性の半導体
上に少なくともTi及びptを順次積層した金J[によ
シ形成されるオーム性電極によシ、高信頼かつ低接触抵
抗を有するオーム性電極を得ることができる効果を有す
るものである。As explained above, according to the present invention, at least lX1
An ohmic electrode with high reliability and low contact resistance formed by gold J[, which is formed by sequentially laminating at least Ti and PT on an n-type conductive semiconductor having a carrier concentration of 0 cm or more. It has the effect of being able to obtain the following.
ジスタの概略断面図である。
1・・・基板、2・・・コレクタコンタクト層、3・・
・コレクタ層、4・・・ベース層、5・・・エミツタ層
、6・・・エミッタ、コンタクト層、7・・・エミッタ
電極、8・・・ベース電極、9・・・コレクタ電極、1
0・・・カバー電極、11・・・保護膜FIG. 3 is a schematic cross-sectional view of a register. 1... Substrate, 2... Collector contact layer, 3...
- Collector layer, 4... Base layer, 5... Emitter layer, 6... Emitter, contact layer, 7... Emitter electrode, 8... Base electrode, 9... Collector electrode, 1
0...Cover electrode, 11...Protective film
Claims (1)
キャリア濃度を有するn型伝導性の半導体上に、少なく
ともTi及びPtを順次積層してなる金属膜を形成した
ことを特徴とするオーム性電極。(1) A metal film formed by sequentially laminating at least Ti and Pt is formed on an n-type conductive semiconductor having a carrier concentration of at least 1×10^1^9 cm^-^3 or more. Ohmic electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12542585A JPS61283120A (en) | 1985-06-10 | 1985-06-10 | Ohmic electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12542585A JPS61283120A (en) | 1985-06-10 | 1985-06-10 | Ohmic electrode |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61283120A true JPS61283120A (en) | 1986-12-13 |
Family
ID=14909780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12542585A Pending JPS61283120A (en) | 1985-06-10 | 1985-06-10 | Ohmic electrode |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61283120A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4957875A (en) * | 1988-08-01 | 1990-09-18 | International Business Machines Corporation | Vertical bipolar transistor |
US5036023A (en) * | 1989-08-16 | 1991-07-30 | At&T Bell Laboratories | Rapid thermal processing method of making a semiconductor device |
-
1985
- 1985-06-10 JP JP12542585A patent/JPS61283120A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4957875A (en) * | 1988-08-01 | 1990-09-18 | International Business Machines Corporation | Vertical bipolar transistor |
US5036023A (en) * | 1989-08-16 | 1991-07-30 | At&T Bell Laboratories | Rapid thermal processing method of making a semiconductor device |
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