JPS61280122A - 2 modulus prescaler - Google Patents

Abstract

PURPOSE:To increase the operating limit frequency and to reduce power consumption by using two-modulus part applying divided by 2/3 variable frequency division as the base for divided by 2<n>/2<n>+1 2-modulus prescalers and constituting the 2-modulus part with two data flip-flops having a 2-data input terminal. CONSTITUTION:When a mode switching signal (m) is at a high level, since a high level signal is fed always to a data input terminal D12a of a DFF 12, outputs q12, the inverse of 12 of the DFF 12 are unchanged, the DFF 11 is operated and outputs q11, the inverse of q11 with a waveform of a period T1 are outputted from output terminals q11, the inverse of q11 to apply 1/2 fre quency division of a clock pulse ck. When the mode switching signal (m) goes to a low level next, the DFF 12 contributes to the frequency division, a non- inverting output q11 of the DFF 11 is read and an inverted output inverse of q12 of the DFF 12 goes to a high level during a period T4. The q11 of the DFF 11 keeps a high level during a period T3 by the said signal, an output during a period T2 is obtained finally and 1/3 frequency division of the clock pulse ck is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a two-modulus greasing scaler, and in particular, the two-modulus scaler has two modulus scalers, in particular 1/2 and 1/3 (hereinafter ÷2) of a clock pulse, corresponding to the logic level of a mode switching signal. 2 modulus part that performs variable frequency division (abbreviated as /3).

(Prior art) 2-modulus glycerano 2-modulus disclosed in Nikkei Electronics June 8, 1981 issue, page 200
The lath circuit is constructed as shown in FIG. 2(a). 1~
3 is data frig float f (hereinafter abbreviated as DFF)
, and 4 and 5 are Noah gates. FIG. 2(b) is a time chart for explaining the circuit of FIG. 2(,), and shows changes in the high and low levels of each terminal in FIG. 2(,). In the circuit of FIG. 2(,), when a clock pulse ck is applied from the output terminal CK of the clock pulse 9, while the high level of the mode switching signal m is applied from the terminal M, the inverted output Q3 of the DFF 3 is applied. is at high and low levels at the period TI (see FIG. 2(b)), which is four times the period of the clock pulse ck.

(See FIG. 2(b)) That is, the frequency of the clock signal ck is divided into 1/4. Furthermore, in the circuit shown in FIG. 2 (-), while the low level of the mode switching signal m is applied from the terminal M, the inverted output Q3 of the DFF 3 goes high and low at the period T2 (see FIG. 2 (b)). The level becomes five times the period of the clock pulse ek (see FIG. 2(b)).

That is, the frequency of the clock signal ck is divided into 115. By dividing the output of this circuit into 1/2 as many times as necessary using a T-7 rig frog, etc.
．． A two-modulus greasing scaler with a frequency division ratio such as ÷128/129 is obtained.

(Problems to be Solved by the Invention) The operating limit frequency of the 2-Moji Elas prescaler is determined by the 2-Moji Elas prescaler portion that performs the frequency dividing operation.

However, as shown in Fig. 2(,), the 2-Mosieras Geliscaler with the above configuration has three DFFs, and it is difficult to reduce power consumption without lowering the operating limit frequency. there were.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a two-mozolar grease scaler that has a high operating limit frequency and can operate with low power consumption.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a plurality of units that perform the same calculation in the two-modulus graticule portion that performs the variable frequency dividing operation of the two-modulus graticule scaler. A first data input terminal and a second data input terminal that are input terminals of one of the plurality of basic logic gates, and a first output that outputs mutually inverted signals. A first DFF and a second DFF having a terminal, a second output terminal, and a clock input terminal are provided, and the first DFF
The first output terminal of the first DFF and the first output terminal of the second DFF are respectively connected to the first data input terminal of the first DFF and the first output terminal of the second DFF.
a first output terminal or a second output terminal of the first DFF is connected to a first data input terminal of the second data flip 70; A clock pulse is applied to the clock input terminal of the second data flip-flop, and a mode switching signal is applied to the second input terminal of the second data flip-flop.

(Function) According to the present invention, as described above, ÷2n/2n+ 1 of 2
Variable division of the monocular prescaler by ÷2/32
Based on the modi lath part, these two modi lath parts are 2
Since it is composed of two data flip-flops with data input terminals, it determines the operating limit frequency.Since there is only a flip-flop in the terminal, the operating frequency can be increased; Since there are only two flip-flops in the modulus part, it is possible to obtain a bimodulus grease scaler with lower power consumption than conventional ones.

(Embodiment) Fig. 1(,) is a circuit diagram of a two-module lath portion for explaining one embodiment of the present invention, and Fig. 1(b) is a circuit diagram of a first
1 is a time chart for explaining the operation of the circuit shown in FIG. FIG. 3 shows an example of the configuration of a DFF having two data input terminals used in the circuit of FIG. 1 (,). This will be explained below along with the drawings.

First, as shown in FIG. 1 (-), 11.12 is a DFF p, the inverted output terminal Qll of oFFxl is connected to the data input terminal DI1m, and the inverted output Q1 of DFF 1.2 is connected to the data input terminal DI1m.
2 is connected to the data input terminal Dllb of the DFF 11, and the non-inverting output terminal Qll of the DFF 11 is connected to the data input terminal Dllb of the DFF 11.
The mode switching signal output terminal M is connected to the data input terminal DI2m of DFF 12, and the clock pulse output terminal CK is connected to the clock input terminals of DFF J 1 and DFF 12. There is.

Next, the operation of the circuit shown in FIG. 1(,) will be explained using FIG. 1(b). ek is clock pulse output terminal C
Clock pulse output from K, qll, qll
.

The output signal outputted from Q12 and m indicate the mode switching signal outputted from the mode switching signal output terminal M, respectively. First, while the mode switching signal m is at a high level, a high level signal is always applied to the data input terminal DI2m of the DFF 12, so the outputs q12 and qlp of the DFF 12 do not change, and the circuit of 0FF11 does not operate. is carried out, and the period T from the output terminals QIZ and Qll
1 waveform output qll, qll is output, and a frequency division operation of 1/2 of the clock pulse ck is performed. Next, when the mode switching signal m becomes low level, DFFz2 contributes to the frequency division operation, reads the non-inverted output qll of DFF 11, and the inverted output q12 of DFF 12 becomes high level during the period T4. This signal #), DFF 11 (D ql
l is maintained at a high level for a period of T3, and an output with a period of T2 is finally obtained, and the clock pulse ck is divided into 1/3.

Next, FIG. 3 shows a circuit diagram of a DFF having two data input terminals used in the circuit of FIG. 1(,). N
31 to N36 are Noah y-h, c is a clock input terminal, and D
a, Db are data input terminals, Q is non-inverting output terminal, Q
is an inverted output terminal. This DFF reads the OR logic of the first data input and the second data input and outputs it at the falling edge of the clock.

As described above, in the embodiment of the present invention, only the frig frozzo is present in the 9th slot of the 2-modulus part that determines the operating limit frequency of the 2-modulus series scaler, so the operating frequency can be increased. In addition, the conventional 2-Mosier Geliscaler has a branching operation of ÷2"/2"+1 divided by 4
15, there are three 7-rig frogs in the 2-modulus part that determines the operating limit frequency, which poses a problem in reducing power consumption. However, in the present invention, based on ÷2/3, ÷2''/2n+1
Since the frequency dividing operation is performed, the 2-modulus part that determines the operating limit frequency can be formed by two DFFs, and
It can be formed by incorporating a basic logic gate into a DFF. Therefore, it is possible to obtain a 2-Moji Elas prescaler with lower power consumption than conventional ones.

In the embodiments of the present invention, the DFF' is formed using a NOR gate, but it can be expected that similar effects can be obtained even if the DFF is formed using other basic logic gates.

(Effects of the Invention) As described above in detail, according to the present invention, a 2-Mosieras Geliscaler with a high operating limit frequency and low power consumption can be obtained.

[Brief explanation of drawings]

FIG. 1(,) shows two diagrams for explaining one embodiment of the present invention.
The circuit diagram of the modulus part, Fig. 1(b), is shown in Fig. 1(,
) is a time chart diagram for explaining the operation of the circuit shown in FIG. 3 is a circuit diagram of the DFF used in the embodiment of the present invention. M...Mode switching signal output terminal, CK...Clock pulse output terminal, O...Output terminal, J, 2
,3,13°14.33.34・OFF,4,5,
31.32-/71"-to, 11.12...OR gate, D...data input terminal, C...clock input terminal, Q...non-inverting output terminal, Q...inverting output terminal , ck...Clock pulse, q...Non-inverting output terminal, q...Inverting output terminal, m...Mode switching signal, N31 to N36...Nor gate.Patent applicant: Oki Electric Industry Co., Ltd. Figure 2 (0) Figure 2 (b) N31-36., /Aγ”4. C+70tsu 2 manpower j
J#1"rDo, Ob: Te'-ta 7F Hanawa), Q: So-reverse Koto-no-han) d: Reverse Miki Karasu J This invention f, the circuit diagram of the rcDFF used in the examples Figure 3 Procedure amendment document (Voluntary) 6Q, 9.25 Showa year month day

Claims (1)

[Claims] A first data flip-flop and a second data flip-flop having a first data input terminal, a second data input terminal, a clock input terminal, and a first output terminal and a second output terminal that output mutually inverted signals. A flip-flop, wherein the first data input terminal and the second data input terminal are input terminals of one basic logic gate among a plurality of basic logic gates forming the first data flip-flop and the second data flip-flop. a first data flip-flop and a second data flip-flop, wherein a first output terminal of the first data flip-flop and a first output terminal of the second data flip-flop are respectively connected to a first output terminal of the first data flip-flop. 1 data input terminal and a second data input terminal; a first output terminal or a second output terminal of the first data flip-flop is connected to a first data input terminal of the second data flip-flop; A clock pulse is applied to the clock input terminals of the first data flip-flop and the second data flip-flop, and a mode switching signal is applied to the second input terminal of the second data flip-flop. 2
Modulus prescaler.