JPS61279933A - Microprogram controller - Google Patents

Abstract

PURPOSE:To simplify writing/reading operations by giving accesses to the same memory contents in different addresses between the writing and reading modes. CONSTITUTION:An address decoder circuit 6 is valid in the reading mode of a control memory device 3 and the device 3 is set under an enable state by an OR circuit 8. Then an address decoder circuit 7 is valid in the writing mode of the device 3. Then the device 3 is set under an enable state by the circuit 8. The circuit 6 decodes a range between an address (1000)16 and an address (IFFF)16, while the circuit 7 decodes a range between an address (3000)16 and an address (3FFF)16.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a microprogram control device.

In particular, the present invention relates to a device for controlling a readable/writable memory (hereinafter referred to as RAM) that stores a microprogram.

[Background of the invention]

Normally, in a data processing device using a microprogram control method, a series of microinstructions are stored in a control storage device, and the microinstructions are sequentially read out and executed by specifying an address in an address register, thereby processing operations such as arithmetic operations. I do. The so-called dynamic program uses the microprogram stored in this control storage device by changing it.
In order to implement microprogram control, it is necessary to use RAM as a control storage device. The configuration of a control storage device for realizing dynamic microprogram control includes the following.

(B) As shown in Figure 4(a), the microprogram for the original instructions of the computer is stored in the ROM 31, and the microprogram for additional instructions and other microprograms for diagnosis are loaded into the RAM 32 as needed. This is what you are trying to do to make it work.

(b) The entire control storage device is composed of RAM.

Among these, there are cases where the main storage device and control storage device are provided separately and independently, and cases where both are shared by the same storage device. (c) It combines a high-speed control memory device, a low-speed control memory device, and a main memory device, and as shown in Figure 4 (b), frequently used microprograms are stored in the high-speed control memory device (RAM). 37, by allocating infrequently used data to the main memory (RAM) 36, the operating speed can be substantially improved. 34
35 is a main memory address register, 35 is a control memory address register, and 38 and 39 are main memory and control memory data registers.

In this way, in microprogram control, RAM is often used as a control storage device, and after reading a series of microinstructions from an external storage device such as a magnetic disk and writing them to the control storage device (RAM), A method is adopted in which these are sequentially read and executed. Also, in the prior art.

There is one set of addresses assigned to the control storage device, and it is common for the control storage device to be accessed by a common address for both reading and writing.

As an example, a microprogram control type processing device is known which is provided with a control storage device 2 for a main processor and a control storage device @3 for a sub-processor as shown in Part 3. In this case, the microprograms for the main processor 2 and the subprocessor 3 are operated by the same microsequencer to control the control storage device. In FIG. 3, control storage! ! When writing data to 2 and 3, the write data is input to the control stores 2 and 3 via gates 13, 14, respectively. What is the write address at that time?

This address is held in the address register 1 and is decoded by the address decoding circuits 9 and 10.
Either control storage 2 or 3 is designated. Here, either control storage device 2 or 3 is specified using 4 bits 1 to 3 of address register 1, and an address for writing/reading to the control storage device specified by the remaining 12 bits is input. In FIG. 3, the control storage device "i, III"'°" of the main processor 2: y-530NJllE'
tl'l&Wl(1)°mtco'sx,.

have. Also, V to the control storage devices 2 and 3
.

By decoding the CS field of the microinstruction register 11 by the decoder 12, the instruction is sent to the control memory 2 of the main processor and the control memory ff of the sub-processor.
13 independently. For this reason, the third
In the device shown in the figure, a decoding circuit 12 is provided in advance on the main processor side, and a designation field (CS field) is required in the microinstruction field. in this way.

Microprogram control schemes with separate control storage require more hardware to write to the control storage. Note that, as shown in FIG. 3, address decoders 9 and 1 are usually provided in the same number as the number of control storage devices, but it is also possible to share these decoders as one decoder [for example, 56-1
See Publication No. 34377].

By the way, in a processing device using a microblock control method, 1. Normally, when a special microinstruction with a large instruction length is defined, the capacity of the control storage device becomes large, and the capacity of the control storage device becomes large regardless of the microinstruction with a short instruction length. The storage device is configured to accommodate large-sized instructions. Therefore, in order to eliminate this inconvenience, some instructions that increase the bit width of control memory are executed only at a certain address width, and the instructions are allocated so that they are not used in other address areas. A device has been proposed to reduce the bit capacity of the control storage device by
(Refer to Publication No.-225438).

As shown in FIG. 5, when storing microinstructions with different instruction word lengths in the control storage device 16, this device places instructions with the same word length at consecutive addresses, and stores instructions with a large length in the A area. In addition, small-length instructions are stored in the B area. by this.

The total pill capacity of the control storage device 16 can be reduced, and an inexpensive processing device can be realized. Among the microinstructions read from the control storage device 16 and latched in the control storage register 17, the oP (operation) part is decoded by the decoder 19 and sent to the arithmetic unit 20, and also connected to the special function circuit 21. be done.

This special function circuit 21 is a logic circuit executed by a special instruction stored in area A of the control storage device 16.

On the other hand, the microprogram sequencer 18 is supplied with the output of the decoder 19, part of the register 17, and the output of the arithmetic unit 20, and one of the three outputs is set as the next control memory address in the control memory bag [16]. is input. However, in the device shown in FIG. 5, when writing a microinstruction to the control storage device 16, a write circuit is required to match the maximum word length of the microinstruction, as in the above example. Of course, when considering reduction in hardware, it is desirable to make this write circuit smaller as well.

[Object of the invention J The object of the present invention is to improve the conventional problems as described above,
To provide a microprogram control device capable of writing microinstructions to a control storage device without increasing the amount of hardware even when the microinstruction word length becomes long only in a specific address range.

[Summary of the Invention] In order to achieve the above object, a microprogram control device of the present invention includes a memory that stores a series of microinstructions;
an address register for holding read/write addresses of the memory; a first address decoding means for decoding the address specified by the address register and writing to the memory; and an address specified by the address register. and a second address decoding means for decoding and reading from the memory, and the second address decoding means for decoding and reading from the memory, and for the same memory contents at the time of fragrance and at the time of reading,
It is characterized by access using different addresses.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a microprogram control device showing an embodiment of the present invention, and FIG. 2 is a block diagram of an address decoding circuit of the control storage device in FIG. 1.

1 and 2 Wi, 1 is an address register, 2 and 3 are control storage devices, 4 and 5 are microinstruction read registers, 6 and 7 are address decode circuits, and 8 is an OR circuit.

In the present invention, an address decoding circuit for reading and an address decoding circuit for writing are provided for control storage devices having partially different microinstruction word lengths, and when writing microinstructions, Writing is performed using a different address than when reading.

In FIG. 1, the main processor side control memory bag W12
A control memory device 3 on the sub-processor side is provided, and a control memory device 2 on the main processor side has a microinstruction word length of 32 bits and is stored from address (0000)18 to (2FFF)18.
The capacity up to the address is unbalanced. Also, the control storage device 3 on the sub-processor side.

It has a microinstruction word length of 32 bits, and the main processor side address (1000)1B to (IFF'F)1
I believe in the capacity that corresponds to number 6. The subprocessor is 1
For example, it becomes valid when a floating point arithmetic instruction is decoded. In other words, floating-point representation is divided into an exponent display section and a mantissa display section, so if the exponent display section is stored in the control storage device on the main processor side, and the mantissa display section is stored in the control storage device on the sub-processor side, , which is convenient for handling during calculations.

The microinstructions read from control stores I\2 and I3 are stored in microinstruction read registers 4.5, respectively. Further, when writing microinstructions to the control storage devices 2 and 3, the microinstructions are transferred to both control storage devices 2 and 3 via the write data bus 9 and written.

In FIG. 2, when reading the control memory bag @3, the address decode circuit 6 is enabled and the OR circuit 8 enables the control memory bag @3. When writing to the control storage device 3, the address decoding circuit 7 is enabled,
Similarly, the control storage device 3 is enabled by the OR circuit 8. The address decode circuit 6 is an address (1000
)1s address to (IFFF)□6 address, and the address decoding circuit 7 decodes the address (3000).
The range from address 16 to (3FFF) 1B is decoded. As a result, the control storage device 3 stores the address (3000) 1 of the control storage device 2 of the main processor during V-loading.
From address 6 to (3F F' F) □ It is considered to exist at address 6. Note that reading 1 to the control storage device 2
, when writing, it is exactly the same as reading and writing to control memory @3.

This is performed by address decoders 6 and 7, but the address range is limited to <o o o o to 2FFF) 1B.

Therefore, for example, the 51st! Control storage device 16 in [
If the instruction word length stored in area A is large (for example,
32+20=52 bits) microinstructions are stored in the control storage device 2 (1000 to I) on the main processor side in the first
P'FF) 1B area and the control storage device 3 on the sub-processor side need to be stored in two areas.
(e.g., 32 bits long)
is (00) of the control storage device 2 on the main processor side in FIG.
゜O~0FFF)16 and (2000~2FFF)1
It is sufficient to store it in area 6. In this case, when writing a microinstruction with a large instruction word length, first select the main processor side with the address register 1, specify address 16 (1000 to IFFF) with the address decode circuit 7, and write the upper part of the microinstruction. 32 bits control storage device 2
After writing to , select the control storage device 3 on the sub-processor side and write (3000
~3FFF) Specify address 1B and write the lower 20 bits of the same microinstruction to control memory @3. Next, when reading this, the control storage device 2 on the main processor side is selected by the address register 1.

By address decoder 6 (toooo~IFFF) 1B
After reading out the upper 32 bits of the microinstruction by specifying , select the control storage device 3 on the sub-processor side using the address register 1, and specify 1e (toooo to 1FFF) as above using the same address decoder 6. The lower 20 bits of the microinstruction are read out. in this way,
When a microinstruction is divided into a basic part and an extended part,
By simply dividing the address decoder into one for reading and one for storing, it is possible to write to the extended part under the same control as for writing to the basic part, so that expansion of the microinstruction word length can be easily handled. Furthermore, when writing microinstructions to the control storage device, it is possible to write with a small amount of hardware, so there is no need to add additional hardware.

〔Effect of the invention〕

As explained above, according to the present invention, in a microprogram-controlled processing device, even if the microinstruction word length becomes long only in a specific address range, writing to the control storage device can be performed without increasing the amount of hardware. and when storing a long instruction in the basic part and extended part, both can be written with the same control, so the control storage device can be easily used for expanding the microinstruction word length. This simplifies the writing/reading process.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprogram control device showing an embodiment of the present invention, FIG. 2 is a connection diagram of an address decoding circuit in the microprogram control device in FIG. 1, and FIG. 3 is a conventional main/sub 2 A block diagram of a microprogram control device equipped with two processors; FIG. 4 is a block diagram of a conventional dynamic microprogram control system;
FIG. 5 is a block diagram of a conventional processing device including a control storage device for storing microinstructions of different word lengths. 1 Near address register, 2, 3, 16, 31° 32.3
7: Control storage device, 4, 5: Microinstruction read register, 6.7: Address decode circuit, 8: OR circuit,
:Figure 1 Figure 2 Figure 3 Cow diagram

Claims (1)

[Claims] (1) A memory that stores a series of microinstructions, an address register that holds read/write addresses of the memory, and a first memory that decodes the address specified by the address register and writes to the memory. It has an address decoding means and a second address decoding means for decoding the address specified by the address register and reading from the memory, and when writing and reading the same memory contents, A microprogram control method characterized by access using different addresses.