JPS6127785B2 - - Google Patents

Info

Publication number
JPS6127785B2
JPS6127785B2 JP57184246A JP18424682A JPS6127785B2 JP S6127785 B2 JPS6127785 B2 JP S6127785B2 JP 57184246 A JP57184246 A JP 57184246A JP 18424682 A JP18424682 A JP 18424682A JP S6127785 B2 JPS6127785 B2 JP S6127785B2
Authority
JP
Japan
Prior art keywords
signal
memory
output
cpu
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57184246A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5972552A (ja
Inventor
Yoshuki Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP18424682A priority Critical patent/JPS5972552A/ja
Publication of JPS5972552A publication Critical patent/JPS5972552A/ja
Publication of JPS6127785B2 publication Critical patent/JPS6127785B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP18424682A 1982-10-20 1982-10-20 デ−タ転送方式 Granted JPS5972552A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18424682A JPS5972552A (ja) 1982-10-20 1982-10-20 デ−タ転送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18424682A JPS5972552A (ja) 1982-10-20 1982-10-20 デ−タ転送方式

Publications (2)

Publication Number Publication Date
JPS5972552A JPS5972552A (ja) 1984-04-24
JPS6127785B2 true JPS6127785B2 (US07816562-20101019-C00012.png) 1986-06-27

Family

ID=16149938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18424682A Granted JPS5972552A (ja) 1982-10-20 1982-10-20 デ−タ転送方式

Country Status (1)

Country Link
JP (1) JPS5972552A (US07816562-20101019-C00012.png)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54939A (en) * 1977-06-06 1979-01-06 Panafacom Ltd Bus priority use control system
JPS5416334B2 (US07816562-20101019-C00012.png) * 1975-10-22 1979-06-21

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5416334U (US07816562-20101019-C00012.png) * 1977-07-06 1979-02-02

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5416334B2 (US07816562-20101019-C00012.png) * 1975-10-22 1979-06-21
JPS54939A (en) * 1977-06-06 1979-01-06 Panafacom Ltd Bus priority use control system

Also Published As

Publication number Publication date
JPS5972552A (ja) 1984-04-24

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