JPS6127646A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPS6127646A JPS6127646A JP14916484A JP14916484A JPS6127646A JP S6127646 A JPS6127646 A JP S6127646A JP 14916484 A JP14916484 A JP 14916484A JP 14916484 A JP14916484 A JP 14916484A JP S6127646 A JPS6127646 A JP S6127646A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- integrated circuit
- lead
- wiring
- silicon chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は集積回路のリード端子を所望位置に配置して、
該集積回路を効率良く利用するための集積回路に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for arranging lead terminals of an integrated circuit at desired positions.
The present invention relates to an integrated circuit for efficiently utilizing the integrated circuit.
電子機器は、電子部材をいちいち配線して組立てる古来
からの方法に代わり、あらかじめ所定の機能を有するよ
うに組立てられた集積回路を採用することによって、コ
ストダウン、生産性とも大幅に向上した。該集積回路の
製造には、設計から完成まで膨大な資金と時間を必要と
する。従って一般ユーザは、メーカから提供される集積
回路から適合した必要なものを選択して使用しているの
である。該集積回路の仕様は全てメーカにおいて決定さ
れているため、所望の機能を有する集積回路であっても
、リード端子の配列が組立において支障を及ぼすことも
ある。Instead of the traditional method of assembling electronic devices by wiring them one by one, electronic devices have greatly reduced costs and improved productivity by using integrated circuits that are pre-assembled to have a predetermined function. Manufacturing such integrated circuits requires a huge amount of money and time from design to completion. Therefore, general users select and use the appropriate integrated circuits from among the integrated circuits provided by manufacturers. Since all specifications of the integrated circuit are determined by the manufacturer, even if the integrated circuit has the desired function, the arrangement of the lead terminals may cause problems in assembly.
即ち、集積回路を使用した電子回路は、各リード線との
配線が最短距離で行なわれることが望ましいものの、例
えば所望の機能端子が配線側と対象位置に配列されてい
るため、わざわざ配線を引廻したり、複数本の配線を交
叉させたりして電子機器の特性を悪くする虞れがある。In other words, although it is desirable for electronic circuits using integrated circuits to have wiring with each lead wire at the shortest possible distance, for example, because desired functional terminals are arranged at the same position as the wiring side, it is not necessary to take the trouble to draw the wiring. There is a risk that the characteristics of the electronic device may be deteriorated by rotating or crossing multiple wires.
よって如何に集積回路を大幅採用した回路も、そのよう
な配線を行なわなければならないのでは、せっかく採用
した集積回路のメリットが充分生かし切れないのである
。又規格化された集積回路の特性は、内部構造を知らな
くとも仕様書を見れば端子の配列に至るまで明らかとな
るので、多大な開発費をかけて完成した電子回路も、市
販の集積回路を用いた場合には容易に模倣、盗用されて
しまう。Therefore, no matter how much integrated circuits are used in a circuit, if such wiring is required, the benefits of the integrated circuits that have been adopted cannot be fully utilized. In addition, the characteristics of standardized integrated circuits can be determined by looking at the specifications, even without knowing the internal structure, down to the arrangement of terminals, so even electronic circuits completed at a great deal of development cost can be compared to commercially available integrated circuits. If it is used, it can be easily imitated or plagiarized.
しかし従来の集積回路は、機能端子の配列のみを組替る
だけでも設計からやり直しているので高価となってしま
い、特別に発注することは余り例がないのである。However, with conventional integrated circuits, even if only the arrangement of functional terminals is rearranged, the design must be redone, making it expensive, and there are few cases of special ordering.
そこで本発明は、従来の集積回路の製造工程において、
シリコンチップの完成までは従来と同様に行ない、その
後の工程でリード端子の各機能を発注に応じた配列に設
定可能としたもので、その構成は、機能端子とリード端
子との結線を、少なくとも一対は対応する端子同士以外
において行なうことにある。Therefore, the present invention provides the following advantages in the conventional integrated circuit manufacturing process:
The silicon chip is completed in the same way as before, and in the subsequent process each function of the lead terminals can be arranged in accordance with the order. The purpose of a pair is to perform the operation at a point other than the corresponding terminals.
次に本発明の実施−例を図面に従って説明すると次の通
りである。Next, embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の集積回路を示したもので、ｌはシリコ
ンチップ、２は該シリコンチップを内装した外囲器であ
る。シリコンチップｌ ｔｔ特定の働きをする回路が組
込まれており、該回路の機能端子３はシリコンチップ１
の外縁に配列されている。一方外囲器２の外周には、電
子機器に使用する場合に配線との接続用のリード端子４
が、前記機能端子と対応する位置に配列されている。以
上の構造については従来の集積回路と異なるところはな
い。FIG. 1 shows an integrated circuit according to the present invention, where l is a silicon chip and 2 is an envelope containing the silicon chip. A silicon chip 1 has a built-in circuit that performs a specific function, and the functional terminal 3 of the circuit is connected to the silicon chip 1.
arranged on the outer edge of On the other hand, on the outer periphery of the envelope 2, there are lead terminals 4 for connection with wiring when used in electronic equipment.
are arranged at positions corresponding to the functional terminals. The above structure is no different from conventional integrated circuits.
従来の集積回路は、前記機能端子３とリード端子４の末
端部４”とが、対応する端子同士を金線又はアルミニウ
ム線によってポンディングしてあって、リード端子はシ
リコンチップの機能端子と全く同一の配列となっている
。当該実施例の集積回路５は、前記ポンディングが対応
する端子間以外（３ａと４ｂ、３ｂと４ａ）で行なわれ
ているため、リード端子の配列は従来の集積回路におけ
る配列と入替っている。このようにしてリード端子の配
列を入替ることにより、電子回路の配線を変更させる。In conventional integrated circuits, the functional terminals 3 and the end portions 4'' of the lead terminals 4 are bonded together using gold wire or aluminum wire, and the lead terminals are completely connected to the functional terminals of the silicon chip. In the integrated circuit 5 of this embodiment, the bonding is performed between the corresponding terminals (3a and 4b, 3b and 4a), so the lead terminal arrangement is different from that of the conventional integrated circuit. By replacing the arrangement of the lead terminals in this way, the wiring of the electronic circuit is changed.
ことが可能となるので、あらかじめ所定の配列となるよ
ラポンデイングの指示を与えれば、容易に希望の集積回
路を得ることができる。該集積回路を使用することによ
って電子機器の配線状態は大幅に向上し、電子回路の解
析も集積回路の組替えたリード端子の配列に惑わされて
容易に行えない。This makes it possible to easily obtain a desired integrated circuit by giving prior instructions for lapping to obtain a predetermined arrangement. By using the integrated circuit, the wiring condition of electronic equipment is greatly improved, and analysis of the electronic circuit cannot be easily performed because it is confused by the rearranged arrangement of the lead terminals of the integrated circuit.
次にリード端子の組替をポンディング以外で行った変更
例を示す。Next, we will show an example of a change in which the lead terminals were rearranged by methods other than bonding.
第２図において、５′は従来の集積回路であって、６は
該集積回路５のリード端子７側に密着して一体化可能な
変換器である。該変換器６の側面には、前記リード端子
７に対応して接触する連結端子８が−Ｌ方に向けて設け
られていると共に、該連結端子８の近接位置に前記リー
ド端子７と対応するリード端子９が下方に向けて設けら
れている。変換器内には連結端子８とリード端子９とが
夫々結線されており、該結線は対応する端子以外（８ａ
と９ｂ、８ｂと９ａ）。In FIG. 2, 5' is a conventional integrated circuit, and 6 is a converter that can be integrated in close contact with the lead terminal 7 side of the integrated circuit 5. A connecting terminal 8 that contacts the lead terminal 7 is provided on the side surface of the converter 6 facing in the -L direction, and a connecting terminal 8 that corresponds to the lead terminal 7 is provided at a position close to the connecting terminal 8. A lead terminal 9 is provided facing downward. Connecting terminals 8 and lead terminals 9 are connected inside the converter, and these connections are connected to terminals other than the corresponding terminals (8a
and 9b, 8b and 9a).
においても行なわれている。従ってリード端子９の機能
は、集積回路５のリード端子７と異った配列となってい
るのである。It is also carried out in Therefore, the functions of the lead terminals 9 are arranged differently from the lead terminals 7 of the integrated circuit 5.
以上の様に構成すれば、市販の集積回路を改造して前記
実施例の集積回路と比べ、より簡単に製造できる。With the above configuration, a commercially available integrated circuit can be modified and manufactured more easily than the integrated circuit of the previous embodiment.
尚本発明において、端子間の結線は、ボンデ ・ボン
デ、変換器以外、外囲器内のリード端子の形状変更によ
っても行なうことが可能であって、その場合、外囲器形
状、ピン配置等、が異なっていて機能を同一とする集積
回路の形成に応用すると、更に本発明の利用範囲が広が
り（第３図参照）、該集積回路の外囲器もＴｏ−５型、
フラットパッケージ型、デュアルインライン型等、その
形状を問うものではない。又変換器を着脱自在に構成し
、変換器を取り外して他の電子機器に正規のピン配置で
従来と同様の使用を可能にしても差支えないのである。In the present invention, the connection between the terminals can also be made by changing the shape of the lead terminals in the envelope other than bonding, bonding, and converters. In that case, the shape of the envelope, pin arrangement, etc. When applied to the formation of integrated circuits having the same function but different .
The shape does not matter, such as flat package type or dual in-line type. Furthermore, the converter may be configured to be detachable, so that it can be removed and used in other electronic equipment with the regular pin arrangement in the same manner as in the past.
以上の如く安価にて要望に応じた設定、変更が可能であ
るため、電子機器の配線を能率良く行なえると共に、電
子回路の模倣防止に役立つのである。As described above, since settings and changes can be made as desired at low cost, wiring of electronic equipment can be done efficiently and it is useful for preventing imitation of electronic circuits.
図面は本発明の集積回路を示したもので、第１図はポン
ディング部における実施例を示す説明図、第２図は変換
器を用いた変更実施例を示す説明図、第３図はリード端
子の形状変更による実施例の説明図である。
１・・シリコンチップ、２．２１１１０外囲器、３．３
ａ、３ｂ−−機能端子、４・暢リード端子、４°・拳末
端部、５・◆集積回路、５′・Φ従来の集積回路、６Φ
・変換器、７・・リード端子、８．８ａ、８ｂ Φ拳連
結端子、９．９ａ、９ｂ・・リード端子The drawings show an integrated circuit according to the present invention; FIG. 1 is an explanatory diagram showing an embodiment in a bonding section, FIG. 2 is an explanatory diagram showing a modified embodiment using a converter, and FIG. 3 is an explanatory diagram showing a modified embodiment using a converter. It is an explanatory view of an example by changing the shape of a terminal. 1. Silicon chip, 2.21110 envelope, 3.3
a, 3b--Functional terminal, 4・Long lead terminal, 4°・Fist end, 5・◆Integrated circuit, 5′・ΦConventional integrated circuit, 6Φ
・Converter, 7...Lead terminal, 8.8a, 8b Φ fist connection terminal, 9.9a, 9b...Lead terminal
Claims (2)
を内装した集積回路を使用する場合に配線と接続するリ
ード端子との結線を、少なくとも一対は対応する端子同
士以外において行ない、前記機能端子の配列とリード端
子の配列とが不一致となるように形成することを特徴と
する集積回路。(1) When using an integrated circuit incorporating the silicon chip, connect the functional terminals of the silicon chip to lead terminals that are connected to wiring at least one pair of terminals other than the corresponding terminals, and arrange the functional terminals. An integrated circuit characterized in that the integrated circuit is formed so that the arrangement of the lead terminals and the arrangement of the lead terminals do not match.
に取付けられていて、該アダプタ内で前記結線が成され
ている特許請求の範囲第１項に記載の集積回路。(2) The integrated circuit according to claim 1, wherein the lead terminal is attached to an adapter coupled to an envelope, and the connection is made within the adapter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14916484A JPS6127646A (en) | 1984-07-18 | 1984-07-18 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14916484A JPS6127646A (en) | 1984-07-18 | 1984-07-18 | Integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6127646A true JPS6127646A (en) | 1986-02-07 |
Family
ID=15469192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14916484A Pending JPS6127646A (en) | 1984-07-18 | 1984-07-18 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6127646A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11413630B2 (en) | 2019-01-31 | 2022-08-16 | Tomoe Engineering Co., Ltd. | Centrifugal apparatus having a bowl with extension lugs and wear-resistant sleeves |
-
1984
- 1984-07-18 JP JP14916484A patent/JPS6127646A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11413630B2 (en) | 2019-01-31 | 2022-08-16 | Tomoe Engineering Co., Ltd. | Centrifugal apparatus having a bowl with extension lugs and wear-resistant sleeves |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH09293822A (en) | Semiconductor device with lead frame for power source only | |
| US5917235A (en) | Semiconductor device having LOC structure, a semiconductor device lead frame, TAB leads, and an insulating TAB tape | |
| US6555923B2 (en) | Semiconductor chip having pads with plural junctions for different assembly methods | |
| JPS6127646A (en) | Integrated circuit | |
| JPS6028256A (en) | Semiconductor device | |
| US5126828A (en) | Wafer scale integration device | |
| JP2629853B2 (en) | Semiconductor device | |
| JP2768111B2 (en) | TAB-Method of Manufacturing Integrated Circuit and TAB Tape for the Method | |
| JPH04129250A (en) | Thin type hybrid integrated circuit substrate | |
| US5869884A (en) | Semiconductor device having lead terminal on only one side of a package | |
| JPH02153557A (en) | Resin sealed type semiconductor device | |
| JPH10303227A (en) | Semiconductor package and its manufacture | |
| JP2000012618A (en) | Semiconductor integrated circuit device | |
| JPH0199245A (en) | Ic package | |
| JPH06326235A (en) | Semiconductor device | |
| JPH06333653A (en) | Ic connecting device for electronic equipment | |
| JPH0325942B2 (en) | ||
| JPH04162735A (en) | Package for semiconductor integrated circuit | |
| JPH10313088A (en) | Semiconductor component, and semiconductor device and manufacture thereof | |
| JPH02164057A (en) | Pin grid array semiconductor package | |
| JPS6081852A (en) | Semiconductor device | |
| JPH08316407A (en) | Manufacture of composite semiconductor package | |
| JPH02195280A (en) | Flat mold package type integrated circuit element | |
| JPS63232437A (en) | Semiconductor device | |
| JPH04365334A (en) | Semiconductor device |