JPS61276429A - Multiplex system for cmi code - Google Patents

Abstract

PURPOSE:To suppress the number of consecutive 1s or 0s to four or below by forming exclusive OR to multiplexed signals at 2-bit each of CMI codes synchronized in plural channels while using a repetitive signal of 1100 of 1-bit delay. CONSTITUTION:An input converting an original signal 1-bit into 2-bit CMI code is given to input terminals 11-13 of a multiplex circuit 2, a CMI code 00 11 01 00... is given to a terminal 11, a CMI code 10 11 00... is given to a terminal 12 and a CMI code 00 11 00... is given to a terminal 13. The signals are multiplexed at 2-bit each and inputted to an input section 21 of a coding circuit 3 in the form of 00 10 00 11 11 11 01 00 00 00.... On the other hand, a scrambler circuit 4 gives a signal of 1 10 01 10 01 10... delayed by 1-bit from the multiplexed CMI code of the circuit 3, which forms exclusive OR of them and outputs an output signal 1 00 01 01 10 01 00 10 01 10... from an output section 31.

Description

[Detailed Description of the Invention] [Summary] In a multiplexing device that includes a multiplexing circuit and an encoding circuit, after multiplexing C old code signals, by constructing an exclusive OR using a logic circuit, 0 Equalization without continuity, timing, discriminable S! ) is a method to obtain multiplexed signals with characteristics.

[Industrial application field]

The present invention relates to an improvement in a CMI code multiplexing method.

When multiplexing and transmitting signals from multiple transmission paths, do not increase the scale of the circuit configuration of the encoder or decoder, and do not cause consecutive 1's or consecutive 0's due to code multiplexing. is desired.

[Conventional technology]

Conventionally, in order to prevent consecutive l's or o's in the code of the original signal, the old C code system is used in which each bit of the original signal is replaced with a 2-bit code of a specific relationship having twice the frequency and then transmitted.

In addition, measures have been taken to prevent continuous l or 0 by converting the unipolar code to a bipolar B8ZS code to eliminate the DC component, applying a scrambler to the unipolar code, and using the mBjC encoding method. There is.

FIG. 3 shows a block diagram of a conventional method for multiplexing CMI codes, and FIG. 4 shows CM! The code signal section is line 1
01.102.103 provides the decoded unipolar code.

Also, the multiplexed output signal is sent to the SC via the output line 201.
Connected to R+88IC encoder.

FIG. 4 shows two examples of combinations of decoder outputs provided to the multiplexer.

That is, the old C code 001101 for the line 101..., 101100... for the line 102, and 00110 for the line 103.
0... is given, from the multiplexer output 201,
A multiplexed signal of 00100011111101000000'... is sent out.

Also, the CMI code 001101... for the line 101, 001100... for the line 102, and 0011 for the line 103.
When 00... is given, a multiplexed signal of 0O000011111101000000... is sent out from the multiplexer output 201.

As is clear from the figure, when CMI codes are multiplexed, l
A series of 0 or a series of 0 occurs, and the thicker the multiplicity, the longer the series (the possibility of it becoming longer) increases.

[Problem that the invention seeks to solve]

The conventional CMI code multiplexing system has the drawback that the configuration of the encoding and decoding circuits is complicated, and the circuit configuration for preventing consecutive l's or 0's is complicated.

[Means for solving problems]

The present invention provides two synchronized CMI codes for multiple communication channels.
A CM that solves the above problems by constructing an exclusive OR of the signal obtained by multiplexing each bit and the 1100 repetition signal delayed by 1 bit! This provides a code multiplexing method.

[Effect]

According to the present invention, each CMI encoded channel signal is
The multiplexing circuit of the direct multiplexing device performs multiplexing processing on every 2 bits of the CI'll code corresponding to 1 bit of the original signal, and the multiplexed signal is transferred to the code conversion circuit of the multiplexing device. By creating an exclusive OR with 1100 repeated signals delayed by 1 bit, it is possible to suppress 1's or 0's to 4 or less consecutively.

〔Example〕

The present invention will be explained in detail below according to illustrated embodiments.

FIG. 1 shows a block diagram of an embodiment of a multiplexing device according to the present invention, and FIG. 2 shows an embodiment of a code conversion process in a code conversion circuit of the multiplexing device.

In the figure, numeral 1 denotes a multiplexing device, which has a multiplexing circuit 2 and an encoding circuit 3, and a scrambler circuit 4 scrambles the multiplexed signal in the encoding circuit 3.

The operation of the multiplexer and the scrambler circuit will be explained with reference to the code conversion process diagram in the encoding circuit shown in FIG.

At the input of the multiplexing circuit, 1 bit of the original signal is converted into 2 bits of C.
Input converted to MI code, as shown - Input terminal 11 has C old code 00110100..., 12 has C
HI code 101100.J., 13 is 001100.
... etc. are given as inputs.

These signals are multiplexed into 2 bits and sent to the encoding circuit 3.
00100011111101000 in the input section 21 of
Input in the form of 0...

According to the invention, the scrambler circuit 4 has its output terminal 4
1, 1 bit later than the multiplexed CMI code
The signals 1001100110 . At this time,
The output signal is 100010f 011001001001
10... is transmitted from the multiplexer l.

〔Effect of the invention〕

The present invention allows the CMI code multiplexing system to be easily realized using a simple scrambler circuit while retaining the old C code, and its effects are extremely large.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of a multiplexing device according to the present invention, Fig. 2 is an embodiment of a code conversion process in an encoding circuit, and Fig. 3 is based on a conventional method of CMI code multiplexing. FIG. 4 is a diagram showing the multi-city process of CMI code signals according to the conventional method. In the figure, 1 is a multiplexing device, 2 is a multiplexing circuit, 3 is an encoding circuit, 4 is a scrambler circuit, IL 12.13 is a C old code input section of multiplexing device l, 3
1 indicates a multiplexed signal output section of the multiplexer 1, 20 indicates a multiplexer, 101.102.103 indicates a C old code input section of the multiplexer 20, and 201 indicates a multiplexed signal output section of the multiplexer 20. .

Claims (1)

[Claims] A signal obtained by multiplexing synchronized CMI codes of a plurality of communication paths every 2 bits of the code, and
A CMI code multiplexing method, characterized in that an exclusive OR with 100 repeated signals is configured.