GB2120054A - Digital data signalling systems - Google Patents
Digital data signalling systems Download PDFInfo
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- GB2120054A GB2120054A GB08310431A GB8310431A GB2120054A GB 2120054 A GB2120054 A GB 2120054A GB 08310431 A GB08310431 A GB 08310431A GB 8310431 A GB8310431 A GB 8310431A GB 2120054 A GB2120054 A GB 2120054A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
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- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
Abstract
Binary or ternary input signals are transmitted on digital data signalling channels in which the ratio of the transmission data rate to the original data rate is an even multiple figure N(4, 6, 8, 10 etc.) or an odd multiple figure M (3, 5, 7, 9 etc.) by encoding each digit of the input signal as N or M binary digits. For even multiple figures binary input signals are represented with one value of the input signal having N DIVIDED 2 digits of value '0' and N DIVIDED 2 digits value '1' in the output signal whilst the other value is represented by N digits of value '0' and N digits of value '1' alternately. For ternary input signals '0' is represented by N DIVIDED 22 digits of value '0' and N DIVIDED 2 digits of value '1' whilst the other two ternary values are represented by N digits of value '0' and N digits of value 1 respectively. For odd multiple figures, one value of a binary input signal or the '0' value of a ternary input signal is represented by M-1 DIVIDED 2 digits of value 0, one digit of value '0' and '1' alternately and M-1 DIVIDED 2 digits of value 1 and the other value of the binary signal is represented by M digits 0 and M digits 1 alternately or the +/- 1 values of the ternary signal are represented by M digits 0 and M digits 1 respectively.
Description
SPECIFICATION
Ditigal data signalling systems
The present invention relates to digital data
signalling systems and in particular, but not exclu sively,to such systemsfortransmission of binary or
ternary encoded data.
Our United Kingdom Patent No. 1,489,177 dis
closes a method of encoding a binary signal in which
direct current and low frequency components are
eliminated.
Our United Kingdom Patent No. 1,489,178 dis
closes a method oftransmitting a binary signal
derived by encoding a balanced ternary signal in which direct current and lowfrequency components
are similarly eliminated.
If the elements of the data signal from which the transmitted binary signal is encoded have a repetition
of, say, eight megahertz since each element in the data signal is represented by two data bits in the transmitted signal,thetransmitted signal will have a transmission rate of sixteen megabits per second.
Accordinglythe original eight megahertz signal when so encoded requires a sixteen megabit data channel.
If a digital data channel is initially provided as being a thirty4wo or a forty megabit channel to allow, say, spare capacity for long term use and/or standardisa- tion of an installation then the relationship between the transmission channel rate and the data rate of the original signal is an integer multiple figure and a simple solution for maintaining the d.c. balance is required.
It is an object of the present invention to provide a method of encoding a digital data stream fortransmission in which the direct current balance ofthe transmitted signal is maintained when the relationship between the transmission rate and the original data rate is an integergreaterthan two.
The term "an odd multiple figure" as used herein means a number in the series (three, five, seven, nine. .) whilst the term "an even multiple figure" means a number in the series (four, six, eight, ten. . .
According to a first aspect of the present invention in a method of encoding a binary input signal for transmission on a digital data signalling channel in which the ratio ofthetransmission rate to the original data rate is an even multiple figure N (as hereinbefore defined) each digit of the input signal is encoded having one value of the binary signal represented by N N bits '0' and N ofvalue '1 'and having 2 2 the other value of the binary signal represented alternately by N bits of value '0' and N bits of value '1' to provide a balanced binary output signal at N times the data rate.
According to a second aspect of the present
invention in a method of encoding a binary input signal for transmission on a digital data signailing
channel in which the ratio ofthetransmission rate to the original data rate is an odd multiple figure M (as
hereinbefore defined) each digit ofthe input signal is
encoded having one value of thebinary signal M-1
represented by bits of value '0'and one bit 2 M-1 alternatelyofvalue '0' and '1'and M bits of value '1' 2
and having the othervalue ofthe binary signal
represented alternately by M bits of value '0' and M
bits of value '1' to provide a balanced binary output
signal at M times the data rate.
Preferably in the method in accordance with the
second aspectofthe invention,the one bit having
alternately the value '0' and '1 ' is centrally located
within the M bits representing the binary signal.
In the method according to the first and seond
aspects of the invention the input binary signal may
be encoded having one binary value being repre
sented buy a pair of digits having the value '01 ' orthe
value '1 0'and having the other binary value being
represented by a pair of digits alternately having the value '00' and '11 ' to provide an intermediate data
stream at twice the original data rate, and the
intermediate data stream is further processed to
provide an output signal at N or M times the original
data rate.
According to a third aspect of the present invention
in a method of encoding a balanced ternary input
signal having digit values of'-1', '0' and '+1'for transmission in binary code on a digital data signall
ing channel in which the ratio ofthetransmission rate
to the original data rate is an even multiple figure N
(as hereinbefore defined) the input signal is encoded
with digits of the input signal having the value '0'
being represented by N digits having the binary
2
value'0' and Ndigits having the binaryvalue'1', and
2
digits of the input signal having the otherternary N
values being represented by N digits having the 2
binary values '0' and '1 ' respectively to provide a
balanced binary output signal at N times the data
rate.
) Accordingtoafourth aspect ofthe present
invention in a method of encoding a balanced ternary
input signal having digitvalues of'-1', '0' and '+1'for transmission in binary form on a digital data signall
ing channel in which the ratio of the transmission rate to the original data rate is an odd multiple figure M (as
hereinbefore defined), the input signal is encoded
with digits of the input signal having the value '0'
being represented bye 1digits having the binary
2
value '0', one digit having the binary values '0' and '1' and M-1digits having the alternately, digits having the binary value '1' 2
and digits ofthe input signal having the othertwo
values being represented by M digits having the
binary value 'land '0' respectively to provide a
balanced binary output signal at M timesthe data rate.
Preferably in the method in accordance with the fourth aspectofthe invention,the one bit having alternatelythevalue'0'and'1' is centrally located within the bits representing the binary signal.
In the method in accordance with the third and fourth aspects of the invention the input signal may be encoded with digits ofthe input signal having the value '0' being represented buy a pair of digits having the binaryvalue '01' orthe binary value '10' and digits ofthe input signal having the othertwo values being represented by a pair of digits having the binary values '11' and '00' respectively to provide an intermediate data stream at twice the original data rate, and the intermediate data stream isfurther processedto provide an outputsignal atN orMtimes the original data rate.
Atransmission system using encoding schemes in accordance with the invention will now be described byway of example with reference to the accompanying drawings of which Figure 1 showsthetransmission system diagrammatically, and
Figure 2 shows pulse waveforms used in the transmission system.
For the purposes ofthis description it is assumed thatthe value of N isfour and the value ofM.is five. It will be appreciated, however, that N may be any even multiple figure and may be any odd multiple figure.
The system to be considered is installed in repeater or other stations of a public telephone network and referring to Figure 1 provides a digital traffic connection between two units 1 and 2which are physically in different stations. As shown, the units 1 and 2 may be digital multiplexing and demultiplexing equipment in which a plurality of inputs at 3 are multiplexed by unit 1 into a digital signal on a path 4 (hereinafter referred to as "a traffic signal"). The digit rate ofthe traffic signal may be ofthe the maybe of eig ht megadigits per second. The unit 2 acceptsthe traffic signal after transmission and performs the inverse operation to that of unit 1 so reproducing the original plurality of input signals atthe inputs 3 as a plurality of output signals atthe outputs 5.
The coding and decoding apparatuses of the system are located adjacent to the units 1 and 2 respectively and are connected by a transmission path 6which may be for example a co-axial line or an optical fibre path.
If the transmission path 6 is arranged to operate with a digital signal of, say,forty megabits per second then it is necessary for a coding circuit7toconvertthe eight megabit persecond input signal to a forty megabit per second output signal.
Thus if the traffic signal signal is a ternary signal and it is to be encoded directlythen the coding circuit 7 operates in the following manner:-Ternary digit values of the traffic signal having the values of "-1" or"+1" are transmitted overthe path 6 as a sequence offive bits having values "00000" or "11111" respectively whilst a ternary digit value of "0" is transmitted as a sequence of five bits having values "00111" on the first and each subsequent odd occurrence ofaternaryvalue "0" and having values "00011 " on the second and each subsequent even occurrence of aternaryvalue"0".
However, if the traffic signal isa binary signal orif the traffic signal has to be decoded from its ternary form to its binary form in orderthat it may be
processed in some way (for example if it is required to scramblethetraffic signal before transmission) then a binary "1" is transmitted overthe path 6 as five bits of value "0" or five bits of value 1 on alternate occurrences ofthe binary 1 and a binary "0" will be transmitted as described above for a ternary "0".
In an alternative method of operation, ifthe input signal is a binary signal each digit is first converted in the manner described in Patent Specification No.
1,489,177 such that if the signal on lead 4 is '0' it is represented in the first stage as '01 'and if the signal on the lead 4 is a binary '1' it is represented in the first stage as '00' and '11' alternately.
Similarly if the input signal is a ternary signal it is converted in the manner described in Patent Specification No. 1,489,178 such that if the signal on the lead 4 is '-1' it is represented in the first stage as '00', '0' on the lead 4 is represented by '01 ' and '+ 1 ' on the lead 4 is represented as '11'.
The encoding of both binary and ternary input signals is identical from here on since each is represented by a sixteen megabit per second data stream having a pair of data bits representing each digitofthe input signal.
Thus as it is necessaryfor each digit of the input signal to the coding circuit 7 to be represented by five data bits in the output signal the two bits of a pair are handled inthefollowing manner: lfthe two bits are identical ('00' or '11') then the system transmits five bits of value '0' orvalue '1' respectively whilst if the two bits are '01 ' the system transmits two bits of value '0', then on the first (and each subsequent odd) occurr ence of'01'one bit of value '0' and on the second (and each subsequent even) occurrence of'01'one bit of value '1' and then two bits of value '1'. It will be appreciated that the single bitofvalue '0' or'1'
alternately may be transmitted beforethetwo bits of value '0' or afterthetwo bits of value '1 whilst
maintaining the d.c. balance.
If nowthe path 6 is arranged to operate atthirty-two megabits per second the traffic signal is encoded in a similarmanneras hereinbeforedescribedexceptthat each digit of the traffic signal is transmitted over the
path 6 as a sequence of four bits. Aternary or a binary
'0' is now encoded as '0011 ' in each case.
In the alternative mode of operation the conversion ofthe input signal is carried out as far as the first stage
hereinbefore described. Subsequently since each bit ofthe input signal is required to be represented by
four data bits each bit of the intermediate data stream
is repeated twice in the outputsignal.
Itwill be realised thatfor even multiple figures (N) ofthe relationship each bit in thefirst stage data
stream is transmitted N times whilst for odd multiple 2 figures (M) the first digit of each pair of digits in the first stage data stream is transmitted Ml(Imes,the 2
second digit of each pair is transmitted M-1 times and
2
the first and second digits of each differing pair are
transmitted alternately.
Decoding by the decoding circuit9 is carried out in
all cases as if the original coding had been performed
in accordance with either United Kingdom Patent No.
1489177 or No. 1489178for binary orternarytraffic
signals respectively. The clock pulse generator pro
duces a clock pulse repetition rate of eight megahertz
only because it is unnecessary to use higher rates to
perform the decoding.
Referring now to Figure 2, waveform A is a typical
binary traffic signal and waveform B a typical ternary
traffic signal.
Waveform C shows the signals of waveforms A and B after conversion to binary two bit code as used in
the intermediate stage of the alternative mode of
operation. Waveforms D and E show waveforms A, B
orCconverted respectivelyfortransmission when N
equals 4 and M equals 5.
Claims (12)
1. A method of encoding a binary input signal for transmission on a digital data signalling channel in which the ratio of the transmission rate to the original
data rate is an even multiple figure N (as hereinbefore
defined) wherein each digit of the input signal is
encoded having one value of binary input signal representedby bits of value '0' and N bits of value
2 2 '1' and having the othervalue of the binary input signal represented alternately byNbits of value '0' and N bits of value '1'to provide a balanced binary output signal at N times the data rate.
2. Amethodofencoding a binary in put signal for transmission on a digital data signalling channel in which the ratio ofthetransmission rate to the original data rate isan odd multiple figure M (as hereinbefore defined) wherein each digit of the input signal is encoded having one value of the binary input signal represented by M-1 bits of value '0' and one bit 2 alternately of value '0' and '1 ' and M 1bits value '1'
2 and having the other value of the binary input signal represented alternately by M bits of value '0' and M bits of value '1' to provide a balanced binary output signal at M times the data rate.
3. A method of encodig a binary input according to Claim 2 wherein the one bit having alternately the value '0' and '1' is centrally located within the M bits representingthe binary signal.
4. A method of encoding a binary input signal as claimed in Claim 1, Claim 2 or Claim 3 wherein the input binary signal is encoded having one binary value being represented by a pair of digits having the value '01'orthe value '1 0' and having the other binary value being represented by a pair of digits alternately having the value '00' and '11 ' to provide an intermediate data stream attwicethe original data rate, and the intermediate data stream is further processed to provide an output signal at NorM times the original data rate.
5. A method of encoding a balanced ternary input signal having digit values of'- î', '0' and '+1'for transmission in binary code on a digital data signalling channel in which the ratio of the transmission rate to the original data rate is an even multiplefigurn N (as herein before defined) wherein the input signal is encoded with digits of the input signal having the value '0' being represented by N digit having the 2 binaryvalue'0' and N digit having the binary value 2 '1', and digits of the input signal having the other ternary values being represented by N digits having the binary value '0' and '1' respectively to provide a balanced binary output signal attimes the original data rate.
6. A methd of encoding a balanced ternary input signal having digit values of'-l','O' and '+l'for transmission in binary form on a digital data signalling channel in which the ratio ofthetransmission rate to the original data rate is an odd multiple figure M as hereinbefore defined wherein the input signal is encoded with digits of the input signal having the
M-1 value '0' being represented by-digits having the
2 binary value '0' one digit having the binary values '0' 'alternately, and having the and '1 digits having the binary 2 value '1' and digits of the input signal having the other two values being represented by Md ig its having the binary values '0' and '1' respectively to provide a balanced binary output signal at times the data rate.
7. A method ofencoding a balanced ternary output signal according to Claim 6 wherein the one bit having alternately the value '0' and '1 ' is centrally located within the M bits representing the ternary value '0'.
8. A method of encoding a balanced ternary inputsignal according to Claim 6, Claim 7 or Claim 8 wherein the input signal is encoded with digits of the input signal having the value '0' being represented by a pair of digits having the binary value '01' orthe binaryvalue'10'anddigitsoftheinputsignal having the other two values being represented by a pair of digits having the binary values '11 ' and '00' respectivelyto provide an intermediate data stream at twice the original data rate and the intermediate data stream isfurther processed to provide an output signal at NorM times the original data rate.
9. A method of encoding a binary input signal for transmission on a digital data signalling channel in which the ratio ofthetransmission rate to the data rate is an even multiple figure (as hereinbefore defined) substantially as hereinbefore described with reference to the accompanying drawings.
10. A method of encoding a binary input signal for transmission on a digital data signalling channel in which the ratio of the transmission rate to the data rate is an odd multiple figure (as hereinbefore defined) substantially as herein before described with reference to the accompanying drawings.
11. A method of encoding a balanced ternary inputsignalfortransmission on a digital data signalling channel in which the ratio ofthetransmission rate to the data rate is an even multiple figure (as hereinbefore defined) substantially as herein before described with reference to the accompanying drawings.
12. Amethodofencodinga balancedternary input signal fortransmission on a digital data signalling channel in which the ratio ofthetransmission rate to the data rate is an odd multiple figure (as hereinbefore defined) substantially as herein before described with reference to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08310431A GB2120054B (en) | 1982-04-23 | 1983-04-18 | Digital data signalling systems |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8211855 | 1982-04-23 | ||
| GB08310431A GB2120054B (en) | 1982-04-23 | 1983-04-18 | Digital data signalling systems |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8310431D0 GB8310431D0 (en) | 1983-05-25 |
| GB2120054A true GB2120054A (en) | 1983-11-23 |
| GB2120054B GB2120054B (en) | 1985-07-31 |
Family
ID=26282636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08310431A Expired GB2120054B (en) | 1982-04-23 | 1983-04-18 | Digital data signalling systems |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2120054B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015095382A1 (en) * | 2013-12-18 | 2015-06-25 | Qualcomm Incorporated | CCIe RECEIVER LOGIC REGISTER WRITE ONLY WITH RECEIVER CLOCK |
-
1983
- 1983-04-18 GB GB08310431A patent/GB2120054B/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015095382A1 (en) * | 2013-12-18 | 2015-06-25 | Qualcomm Incorporated | CCIe RECEIVER LOGIC REGISTER WRITE ONLY WITH RECEIVER CLOCK |
| CN105830045A (en) * | 2013-12-18 | 2016-08-03 | 高通股份有限公司 | Ccie receiver logic register write only with receiver clock |
| US10031547B2 (en) | 2013-12-18 | 2018-07-24 | Qualcomm Incorporated | CCIe receiver logic register write only with receiver clock |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2120054B (en) | 1985-07-31 |
| GB8310431D0 (en) | 1983-05-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |