JPS61276373A - Manufacturing process of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an FET structure from being broken by the bridge connection between Ti silicide portions, by covering the exposed faces of a gate electrode with a chemically inactive insulating material before adhering high-melting metal layers on source and drain regions and silicifying the metal. CONSTITUTION:A field oxide layer 22 is grown on a semiconductor substrate 21. A gate oxide film 23, a poly Si layer 24, a Ti silicide layer 25 and an Si dioxide layer 26 are formed on the most region. The layers are then patterned by etching so as to form a gate electrode E. The exposed faces of the gate electrode E are covered with a cap oxide film 28. An impurity is implanted to form source and drain regions 29. The whole surface is then covered with a layer of high-melting metal or Ti 210, which is heated to a high temperature so that the Ti layer portions 210 located on the regions 29 are converted into Ti silicide 211. The layers 22 and the oxide 28, which are not silicified, are removed selectively by etching while the Ti silicide layers on the regions 29 are left. According to the method as described above, the FET structure can be effectively prevented from being broken by the bridge connection between the Ti silicide on the electrode E and the Ti silicide on the regions 29.

Description

[Detailed description of the invention] <Industrial application field> The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device.

The present invention relates to a method of manufacturing a semiconductor device in which a high melting point metal silicide is formed on a gate electrode and source/drain regions to reduce the resistivity of the electrodes and source/drain, thereby increasing the speed of signal transmission.

<Conventional technology> When the pattern size of a semiconductor device is made finer, the switching characteristics of a single transistor usually improve according to the scaling law, but in integrated circuits, due to the increase in wiring resistance, it becomes difficult to send signals to transistors far from signal input terminals. The transmission of data was delayed, making it impossible to improve the operating speed of the integrated circuit. As a result, there has been a demand for lower wiring resistance, and salicide gates have come into use.

The process for manufacturing such a salicide gate will be described with reference to FIG. 2. A field oxide layer 2 is formed on a semiconductor substrate 1 to define a moat region (FIG. 2(a)). Next, a gate oxide film 3 is grown by thermal oxidation (see Fig. 2).
b) ), depositing a polysilicon layer 4 thereon (
After that, a gate electrode E having a predetermined pattern is formed by etching (FIG. 2(d)).
.

A silicon dioxide layer 6 is deposited again (FIG. 2(e)).
), a sidewall 7 with a width of about 2008 to 3000 mm is formed surrounding the gate electrode E by anisotropic etching (FIG. 2(f)), and impurities are implanted into the source region 8 and drain region 8. After lateral diffusion of impurities by heating and alignment of the end of the channel region with the source region 8 and each end of the region (see FIG. 2(g)).
), a high melting point metal such as titanium is deposited to form a titanium layer 9 (FIG. 2(h)), and then
Titanium is reacted with the polysilicon forming the gate electrode E and the silicon substrate forming the source/drain region 8 by sintering by high-temperature heating, and titanium silicide (TiSi2) is formed on the gate electrode E and the source/drain region 8, respectively. ) 10 (Figure 2 (i
)).

On the other hand, since the titanium layer 9 in contact with silicon dioxide is not silicified, the titanium on the field oxide layer 2 and the sidewall 7 does not become titanium silicide, and the portions other than the titanium silicide portion 10 are removed by selective etching. (Fig. 2 (j)), and then.

Necessary wiring is provided and the entire structure is covered with a protective layer of insulator.

Therefore, the electrode E and source/drain region 8 through which signals are transmitted have a double structure containing titanium silicide, and since the specific resistance of titanium silicide is significantly smaller than that of polysilicon, etc., the integrated circuit operates. The speed will be improved.

<Problems with the prior art> However, in the conventional semiconductor device manufacturing method, the titanium silicide portion lO on the electrode E and the titanium silicide portion 1o on the source/drain region 8 are formed from the same titanium layer 9 by high temperature heating. , were formed at the same time, the silicon in the titanium silicide formed on the electrode E and the source/drain region 8 diffused into the titanium layer 9 and exposed in the sidewall 7.

In severe cases, as detailed in FIG.
There is a problem in that the upper titanium silicide portion 10 and the titanium silicide portion 10 on the source region 8 or the drain region 8 are bridged, destroying the structure of the field effect transistor.

Means for Solving the Problems> In view of the destruction of the field effect transistor structure due to the bridging of the titanium silicide portion 10, the present invention provides a method for reducing the exposed portion of the gate electrode composed of a conductive semiconductor and a metal silicide layer. <Embodiment> The gist is to deposit a high melting point metal layer on the source region and the drain region after covering them with a chemically inert insulator, and to silicify the layers. FIG. 1 shows one example of the present invention. 1 is a diagram showing an example, and the manufacturing process of a semiconductor device will be described below with reference to the diagram.

First, a field oxide layer 22 is grown on a semiconductor substrate 21 by thermal oxidation to define a moat region (see FIG.
)). Next, a thin gate oxide film 23 is formed on the moat region by thermal fermentation (FIG. 1(b)), and a polysilicon layer 24, a titanium silicide (TiSi2) layer 25, and a silicon dioxide layer 26 are formed on top of it. (Fig. 1(C) to (e)
) ), the titanium silicide layer 25 is formed by a sputtering method, and the sputtering is a mixed crystal target layer) (TiSix
) Alternatively, sputtering using a mosaic target may be used, or a co-sputtering method using a titanium target and a silicon target in combination may be used.

Thereafter, a gate electrode E is formed by a pattern forming process by etching (FIG. 1(f)), and silicon dioxide 27 is deposited again by low pressure chemical vapor deposition (first step).
Figure (g)), gate electrode E is formed by anisotropic etching.
As a result of anisotropic etching, a cap oxide 2B is formed to cover the exposed parts of the silicon substrate 2 (FIG. 1(h)).
1 is exposed in the moat region, impurities are implanted into the source region 28 and drain region 28,
Through a lateral thermal diffusion step, the end of the gate electrode E and each end of the source region 29 and drain region 28 are aligned (FIG. 1(i)). In the next step, titanium is sputtered to cover the entire surface with a titanium layer 210 (first
(J), high temperature heating causes a chemical change in the titanium layer 210 in contact with the silicon substrate 21, changing the titanium layer 210 on the source region 29 and drain region 29 to titanium silicide 211. Field oxide layer 22 and cap oxide 28 comprised of silicon dioxide
is chemically stable, and the titanium layer 210 in contact with these does not become silicified, so it is removed by selective etching, leaving titanium silicide on the source region 28 and drain region 28 (FIG. 1(k)). . After this, the semiconductor device is completed by patterning the metal wiring and depositing the protective oxide film. As described above, according to the present invention.

After covering the exposed part of the gate electrode consisting of a conductive semiconductor layer and a high melting point silicide layer with a chemically inert insulator,
Since a high melting point metal layer is placed on the source region and the drain region and the high melting point metal is silicified, when forming the high melting point silicide on the source region and the drain region, these layers are The high melting point silicide and the high melting point silicide constituting the gate electrode are insulated by a chemically inert insulator, and the effect of preventing bridging between these high melting point silicides can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a process diagram showing an embodiment of the present invention, FIG. 2 is a process diagram showing a conventional manufacturing method, and FIG. 3 is a partially enlarged cutaway diagram of a semiconductor device manufactured by the conventional method. 21... Semiconductor substrate, 23... Gate insulating layer, 24...
...Conductive semiconductor layer (polysilicon layer) 25...
......High melting point metal silicide layer (titanium silicide layer) E......Gate electrode, 28......Chemically inert insulator (cap oxide 28... Source region and drain region, 210... High melting point metal layer (titanium layer)
. Patent applicant: Japan Texas Instruments Co., Ltd. Figure 3 CI Group

Claims (1)

[Claims] A step of superimposing a gate insulating layer 23 and a conductive semiconductor layer 24 on the semiconductor substrate 21, a step of laminating a high melting point metal silicide 25 on the conductive semiconductor layer 24, and a step of stacking the gate insulating layer 23 and the conductive semiconductor layer 24. The layer 24 and the refractory metal silicide layer 25 are simultaneously patterned to form the gate electrode E.
, a step of covering the exposed portion of the gate electrode E with a chemically inert insulator 28 , and a step of forming a high melting point metal layer 210 on the source region 29 and drain region 29 formed on the surface of the semiconductor substrate. Deposition process and high melting point metal layer 21
A manufacturing process of a semiconductor device including a process of silicifying 0.