JPS61276368A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent damage accompanying ion implantation and to obtain a low-noise and high-speed Si device, by providing with a single crystalline Si layer with the same crystal orientation as the substrate, in an insulating opening section on the Si substrate. CONSTITUTION:An opening 23 is bored through the thick oxide film 22 on the N-type Si substrate 21. With plasma reaction of SiH4, a thin amorphous Si layer 24 is deposited on the entire fade, and then B ions are implanted into the layer 24. If the doping into the amorphous Si is done in excess of the soluble limit, it wound result in defects being created in the course of the crystallizing process. Next, heat treatment for one hour at 600 deg.C in inert gas causes a single crystalline layer 25 to grow from the interface between the substrate 21 and the amorphous Si layer 24, and converts the amorphous layer 24 lying on the oxide film 22 into a poly Si layer 26. In this way, since B ions are implanted after the amorphous Si layer 24 is formed, damage owing to the ion-implantation does not remain in the substrate, and disturbance of carriers at crystal again boundaries does not exist because polysilicon is not used as in prior arts. Accordingly, a low-noise device can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and is particularly used for forming low-noise, high-speed semiconductor elements.

[Technical background of the invention and its problems]

Conventionally, semiconductor devices have been manufactured as shown in FIGS. 2(a) and 2(b), for example. First, a thick oxide film 2 is formed on a silicon substrate 1, and then the oxide film 2 is removed by selective etching to form an opening 3. Subsequently, a thin oxide film 4 is formed in this opening 3. Next, ions are implanted into the entire surface (as shown in FIG. 2(a)). In addition, the same figure (a)
In the substrate 1 directly under the thin oxide film 4, a cine blunt layer (marked with an x) is formed by the aforementioned ion implantation.

Thereafter, heat treatment is performed to form the substrate IK diffusion layer 5 directly under the thin oxide film 4, and a semiconductor device is manufactured (as shown in FIG. 2(b)).

However, according to the prior art described above, damage caused by ion implantation is attempted to be reduced by interposing a thin oxide film 4, but the ion implantation damaged portion in the substrate 1 is fully recovered by subsequent heat treatment. do not. In particular, recent high-speed devices have shallow junction depths, making it difficult to apply sufficient heat treatment time and temperature to recover from implantation damage.

Specifically, when impurity ions are implanted into the silicon substrate 1, the crystal lattice of the Si single crystal is distorted and disordered, and point defects and planar defects are likely to remain even after crystal recovery by heat treatment. When such defects exist in the active region of a transistor, they disrupt and inhibit the flow of carriers and become a source of noise. Therefore, in order to prevent these defects from remaining, low-temperature annealing at 600 to 800°C is performed, followed by high-temperature annealing (
Efforts have been made, such as heat treatment at a temperature of 1100°C or higher. However, in order to obtain a shallow bond, high temperature heat treatment is required.
Since the treatment is carried out at a relatively low temperature and for a short period of time, such as at 0° C. for 30 minutes, sufficient crystal recovery is often not achieved.

Further, a conventional semiconductor device is shown in FIG. 3(a), for example.

It is manufactured as shown in (b). First, a thick oxide film 2 was formed on a silicon substrate 1, an opening 3 was formed therein, and then a polycrystalline silicon layer 6 was formed thinly over the entire surface. Subsequently, impurity ions are implanted into the polycrystalline silicon layer 6 (as shown in FIG. 3(, )). Note that during this ion implantation, damage to the substrate 1 can be avoided due to the presence of the polycrystalline silicon layer 6. Next, impurities in the polycrystalline silicon layer 6 in the opening 3 were diffused into the substrate 1 by heat treatment to form a diffusion layer 5, and a semiconductor device was manufactured (as shown in FIG. 3(b)). However, according to this method, when forming the paste of the bipolar transoster, the subsequent emitter must be formed in the polycrystalline silicon layer 6, and a polycrystalline silicon layer is formed on a part of the emitter-paste junction surface. 6, the grain boundaries of polycrystalline silicon are a source of noise.
It cannot be applied to actual devices.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can avoid damage caused by ion implantation into a semiconductor substrate and can obtain a low-noise, high-speed semiconductor element. shall be.

[Summary of the invention]

A first invention of the present application includes a semiconductor substrate, an absolute R film provided on the semiconductor substrate and having an opening, and an absolute R film provided on the semiconductor substrate exposed from the opening and having the same crystal orientation as the substrate. It is characterized by comprising a single crystal layer.

The second invention of the present application includes a step of forming an insulating film on a semiconductor substrate, a step of selectively removing the insulating film to form an opening, and forming an amorphous semiconductor layer containing impurities on the entire surface. and a step of heat-treating the amorphous semiconductor layer to form a single crystal layer having the same crystal orientation as the substrate from the amorphous semiconductor layer that contacts the semiconductor substrate at the opening. Features.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 Refer to FIG. 1 (a) s (b) t. First, for example, on an N-type single crystal silicon substrate 21, a thickness of about 6000× is formed.
A thick oxide film 22 was formed. Subsequently, this thick oxide film 22 was selectively removed to form an opening 23. Next, a thin amorphous silicon layer 24 with a thickness of 3000× was formed on the entire surface by a plasma reaction of SiH4 gas at 300° C. using a plasma-CVD method. Thereafter, boron was introduced into the thin amorphous silicon layer 24 at an accelerating voltage of 30 KaV.
Ion implantation was performed under the following conditions: I:fkI x 1014 cm 20 (as shown in FIG. 1(,)). Note that the amount of impurity doped into the amorphous silicon layer 24 is limited by the solid solubility limit in St, and doping exceeding the solid solubility limit causes defects in the crystallization process.

Furthermore, solid phase epitaxial growth (heat treatment) of the amorphous silicon layer 24 was performed. This heat treatment is carried out at a temperature of, for example, 6
The test was carried out at 00°C for 1 hour in an inert gas atmosphere. As a result, single crystal growth occurs from the interface between the single crystal silicon substrate 2 and the amorphous silicon layer 24 in the opening 23 to form the single crystal silicon layer 25, and the amorphous silicon layer on the thick oxide film 22 is formed. 24 is a polycrystalline silicon layer 26, and a semiconductor device is manufactured (as shown in FIG. 1(b)).
According to , an amorphous silicon layer 25 is formed on an N-type silicon substrate 21 through a thick oxide film 22 having an opening 23, and after ion implantation of Zarron at a low concentration under predetermined conditions. Since heat treatment is performed, a single crystal silicon layer 25 having the same crystal orientation as the substrate 21 can be formed only on the substrate 21 in the opening 23. Therefore, it has the following effects.

(2) Since poron ion implantation is performed after forming the amorphous silicon layer 24, it is possible to avoid damage remaining in the substrate 21 due to the poron implantation as in the conventional method. The sagging occurs because even if poron is implanted into the amorphous silicon layer 24, no defects occur in the amorphous silicon layer 24, which originally has no crystallinity. This is because the crystals are rearranged to have good consistency with the silicon substrate 21, and defects such as implantation damage do not occur.

- Since a polycrystalline silicon layer is not used as in the conventional method, there is no disturbance of carriers at grain boundaries, and a low-noise device can be formed.

As shown in FIG. 1(b), the semiconductor device according to the first embodiment has a contact portion 23 on an N-type single crystal silicon substrate 2.
A thick oxide film 22 having a
It has a structure in which a single crystal silicon layer 25 having the same crystal orientation as the substrate 21 is provided on the substrate 21 exposed from the substrate 21. Therefore, as described above, it is possible to prevent defects from occurring in the substrate 21 and to form a low-noise element.

In Example 1, a case was described in which poron was ion-implanted into the amorphous silicon layer at a low concentration, but the invention is not limited to this. Poron ions may be implanted into the amorphous silicon layer 24 at a high concentration and diffused into the substrate. May be used as a source. In addition, atoms such as phosphorus, arsenic, antimony, etc. may be used as impurities, not limited to silica. Furthermore, although the amorphous silicon layer was partially made into a single crystal by the heat treatment at the low temperature described in 1 above, the present invention is not limited thereto. That is, after forming an amorphous silicon layer, S
It is also possible to cover the i3N4 film and irradiate it with upper color redeannealing to cause sheer vitaxial growth to form a single crystal.

Example 2 An example of application to an NPN transistor is shown in Figures 4(,) to (6).
).

First, a high concentration (
After forming a buried layer 31 of (N+W), an evitacal layer 32 of Nu was formed. Subsequently, P-type impurities were appropriately diffused into the epitaxial layer 32 by a conventional method to form a P-type isolation region 33 and an N-type collector extraction region 34 (see FIG. 4). a) As shown).

Next, as in Example 1, after forming a thick oxide film 22 having openings 23, an amorphous silicon layer 24 was formed (as shown in FIG. 4(b)). After that, this amorphous silicon layer 24 is appropriately turned, and the poron is heated to an accelerating voltage of 3.
Ion implantation was performed under the condition of a 5 Kev1 dose of 5×10 cm (as shown in FIG. 4(c)).

Next, the amorphous silicon layer 24 is heat-treated under the same conditions as in Example 1 to form a single crystal silicon layer 25 on the substrate 21 of the contact portion 23, and another amorphous silicon layer 24t-polycrystalline silicon layer 25 is formed on the substrate 21 of the contact portion 23. It was set as layer 26. Subsequently, by performing diffusion at 1150 C for 50 minutes using the single crystal silicon layer 25 as a diffusion source, a P-type space region 35 with no crystal defects and a specific resistance of 180 Ω and a depth of 2.5 μm was formed. 4
Figure (d) (illustrated). Next, apply cvnsto□ to the entire surface, for example.
After forming the film 37, the CVD 5in2 film 37 corresponding to a portion of the space area 35 was selectively removed. Furthermore, a polycrystalline silicon layer 3gt containing n-type impurities on the entire surface
- An N-type emitter region 39 was formed on the surface of the space region 35 by deposition and diffusion to produce an NPN transistor (as shown in FIG. 4(a)). Note that the wiring can be formed by opening a hole in a desired contact area and forming an electrode using a conventional method.

According to the second embodiment, an amorphous silicon layer 24 is formed on a P-type silicon substrate 21 on which a buried layer 31, an epitaxial layer 32, etc. are formed, through a thick oxidized MX 22 having an opening 23. Formation, -'4 turning and further? Since heat treatment is performed after ion implantation of ions at a high concentration under predetermined conditions, a single crystal silicon layer 25 having the same crystal orientation as that of the substrate 2 can be formed only on the substrate 21 of the contact portion 23. Moreover, this single crystal silicon layer 25
By using K as a diffusion source and diffusing under predetermined conditions, a P-type base region 34 without crystal defects can be formed. Furthermore, according to the method rC described above, there is no disturbance of carriers at grain boundaries, and a low-noise device can be formed.

In fact, the NPN transistor according to the second embodiment (fourth
According to Figure (e), the burst noise generation rate is approximately 10% in the conventional ion implantation method into a silicon substrate.
A significant noise generation rate reduction effect of 1% or less was observed. Furthermore, when the long profile of the single crystal silicon layer 25 is measured, as shown in FIG. When used in a wide area, the electric field gradient becomes much flatter), making it effective for high-speed operation. In addition, the fifth
In the figure, 0) shows the ron profile curve at-1 (b) according to the present invention, and the ron profile curve at-1 (b) shows the 7-isle curve according to the conventional method.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the same, which can avoid damage to the surface of a semiconductor substrate and can obtain a low-noise, high-speed semiconductor element.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are cross-sectional views showing the manufacturing method of a semiconductor device according to Example IK of the present invention in the order of steps, and FIG.
) #(b) is a cross-sectional view showing a conventional method for manufacturing a semiconductor device in order of steps, FIG. 3(a) #(b) is a cross-sectional view showing another conventional method for manufacturing a semiconductor device in order of steps, FIG. (
a) to (,) are cross-sectional views showing the manufacturing method of the NPN Lansostar according to Example 2 of the present invention in the order of steps, and FIG. 5 is a characteristic diagram showing the relationship between the junction depth and the impurity concentration according to the conventional method and the present invention. . 21... P-type single crystal silicon substrate, 22... Thick oxide film, 23... Opening portion, 24... Amorphous silicon layer, 25... Single crystal silicon layer, 26.38 . . . Polycrystalline silicon layer, 31 . . . Embedded layer of joint type, 32 .
- N type epitaxial layer, 33... P type isolation region, 34... N type collector extraction region, 35... P type base region, 36... CvDSI
O2 film, 39...N type emitter region. Applicant's agent Patent attorney Takehiko Suzue wE4 Figure

Claims (3)

[Claims] (1) A semiconductor substrate, an insulating film provided on the semiconductor substrate and having an opening, and a single crystal layer provided on the semiconductor substrate exposed from the opening and having the same crystal orientation as the substrate. A semiconductor device comprising: (2) A step of forming an insulating film on a semiconductor substrate, a step of selectively removing this insulating film to form an opening, a step of forming an amorphous semiconductor layer containing impurities over the entire surface, and A semiconductor device comprising the step of heat treating an amorphous semiconductor layer to form a single crystal layer having the same crystal orientation as the substrate from the amorphous semiconductor layer that contacts the semiconductor substrate at an opening. manufacturing method. (3) The method for manufacturing a semiconductor device according to claim 2, characterized in that a silicon substrate is used as the semiconductor substrate, and an amorphous silicon layer is used as the amorphous semiconductor layer.