JPS61274457A - Detecting circuit for phase error - Google Patents

Abstract

PURPOSE:To realize a detection of high accuracy by detecting a phase difference using a phase locked circuit synchronized with a phase change component which depends upon each of different transmission data patterns with each other in an inputted digital modulating signal. CONSTITUTION:The first phase locked circuit 7 is synchronized with a phase component which depends upon the first transmission data pattern in the inputted digital modulating signal out of phase informations outputted from a conversion table 5 and the second phase locked circuit 8 is synchronized with the second phase change component synchronized with the second transmission data pattern in the inputted digital modulating signal. A phase error arithmetic circuit 9 calculates the phase error from the output signals of these first and second phase locked circuits 7 and 8. The phase locked circuits 7 and 8, after a phase lock is once settled, operate in the same manner so that the same signal is inputted to these circuits. Therefore, it is possible to detect a clock phase error accurately than ever.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a circuit for detecting a phase error of a recovered clock used in receiving and demodulating a digitally modulated signal.
In particular, it relates to a phase error detection circuit using digital signal processing.

[Technical background of the invention and its problems]

In recent years, digital ICs and microprocessors.

With the advancement of LSIs for digital signal processing, digital signal processing, which has features such as high functionality, system expandability, and high stability, has come to be used in various fields. For example, in the field of electronic communications, digital signal processing is increasingly used in modulation/demodulation circuits.

When applying digital signal processing, a major issue is how to increase the processing speed. especially,
There is a strong demand for this in demodulation circuits that handle modulated signals using digital modulation methods such as MSK and PSK. In other words, when configuring a demodulation circuit using digital processing, if the sampling clock (regenerated clock) used when converting the input modulated signal into an analog signal with an A/D converter is not synchronized with the transmission clock, the Since malfunctions in the demodulation system due to phase errors increase at an accelerating rate, it is necessary to establish phase synchronization of the reproduced clock as quickly as possible, and the demand for high-speed operation is stronger than in demodulation circuits using analog signal processing.

However, in conventional demodulation circuits using digital signal processing, the input modulated signal is converted into a digital signal by an A/D converter, and then demodulated by processing the amplitude value using trigonometric function formulas. Therefore, a multiplier was required as a component, which was an obstacle to increasing speed. Further, the multiplier is a basic calculation element with the largest circuit scale in a digital circuit, and using a large number of multipliers is not desirable in terms of hardware reduction.

Furthermore, in conventional demodulation circuits using digital signal processing, the phase error of the recovered clock is detected by detecting the zero-crossing point of the demodulated data. It is completely impossible to detect a phase error, and during this period, the phase of the reproduced clock is in a free-run state, resulting in a problem in that synchronization is likely to occur.

[Purpose of the invention]

It is an object of the present invention to provide a phase system that is capable of high-speed operation, reduces the overall circuit scale, and can efficiently detect the phase error of the recovered clock even when the transmitted data pattern is unfavorable for detecting the phase error of the recovered clock. An object of the present invention is to provide an error detection circuit.

[Summary of the invention]

In order to achieve this object, the present invention inputs a pair of digital signal sequences having a quadrature phase relationship obtained by sampling a digital modulation signal using a regenerated clock,
a converting means for outputting phase information as a digital signal corresponding to a combination of digital values representing the amplitudes of the pair of digital signal sequences at each time; a first phase synchronization circuit that synchronizes with a first phase change component depending on the first transmission data pattern; dependent second
a second phase synchronized circuit that synchronizes with the phase change component of the digital modulation signal; and a phase error calculation circuit that calculates the phase error of the reproduced clock with respect to the transmission clock of the digital modulation signal from the output signals of the first and second phase synchronized circuits. It is characterized by having the following.

〔Effect of the invention〕

According to the present invention, the input digital signal sequence, which is amplitude value information, is converted into phase information by the conversion means, and the phase error of the reproduced clock is detected from the phase information. Therefore, calculations for detecting the phase error are basic. This can be realized by processing mainly based on addition and subtraction, without requiring multiplication.

Therefore, compared to conventional circuits that calculate phase errors by multiplying amplitude values using trigonometric formulas, processing speed can be increased, making it possible to introduce digital signal processing into high-speed digital communication systems. becomes. Further, since the number of multipliers is unnecessary or reduced, the overall circuit scale can be significantly reduced.

Broadly speaking, in the present invention, in order to detect the phase error of the recovered clock from the output signals of the first and second phase synchronization circuits that are synchronized with the phase change components depending on different transmission data patterns in the input digital modulation signal, Phase errors can always be detected, and detection can be performed with higher precision.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention.

In the figure, a pair of signals having an orthogonal phase relationship obtained by orthogonally transforming a digital modulation signal on the receiving side are input to terminal 1.2, and are converted into a digital signal sequence by an A/D converter 3.4. After that, it is input into the conversion table 5. The conversion table 5 is configured using, for example, a ROM table,
Phase information corresponding to a combination of digital values representing the amplitude at each time of a pair of input digital signal sequences is output as a digital signal. That is, if the input signal series of the conversion table 5 are x and y, then jan'
(X/Y) polar coordinate transformation is performed.

The output signal of the conversion table 5 is guided to a synchronous demodulation circuit (not shown) and is also input to a phase error calculation circuit 6 based on the present invention. This phase error calculation circuit 6 is a circuit that detects the phase error of the recovered clock with respect to the transmission clock of the input digital modulation signal, that is, the sampling clock to the A/D converter 3.4, and is a circuit that detects the phase error of the sampling clock to the A/D converter 3.4. It is composed of a circuit 7.8 and a phase error calculation circuit 9.

The first phase synchronization circuit 7 synchronizes with the phase component of the output phase information of the conversion table 5 that depends on the first transmission data pattern of the input digital modulation signal, and the second phase synchronization circuit 8 synchronizes with the phase component dependent on the first transmission data pattern of the input digital modulation signal. The second phase change component is synchronized with the second transmission data pattern of the modulated signal.

The phase error calculation circuit 9 calculates a phase error from the output signals of the first and second phase synchronization circuits 7.8.

The phase error signal output from the phase error detection circuit 6 has its noise component removed by the loop filter 11, and then is converted into an analog voltage by the O/A converter 12, and is used as a control input of the voltage controlled oscillator (VCO) 13. Become. A reproduced clock synchronized with the transmission clock of the input digital modulation signal is obtained at the output of the VCO 13, and this is supplied to the A/D converters 3 and 4 as the sampling clock 14.

Next, the configuration of the phase error detection circuit 6 will be described in detail, taking as an example the case where the digital modulation signal input to the terminal 1.2 is frequency-converted to baseband and is an MSK signal that is orthogonally expanded. FIG. 2 shows the configuration of the first phase locked circuit 7 in this case.

The signal input to terminal 1 is expressed as , and the signal input to terminal 2 is expressed as . Here, a, 1 is +1 or -1 transmission data, Δ
t is the phase error of the reproduced clock, Δθ is the phase error of the reproduced carrier, and T is the symbol rate. When these signals are input to the conversion table 5, the output of the conversion table 5 is expressed as. The value expressed by formula (3) is 3 in Figure 3.
01-309. As you can see from this diagram, MSK
The signal has a positive phase change component such as 302→303 and a negative phase change component such as 304→305.

The output signal of this conversion table 5 is transmitted to the phase error detection circuit 6.
is input to the first and second phase synchronization circuits 7.8. In the first phase synchronization circuit 7, as shown in FIG. 1, 2, 3, 0, 1, 2, 3,・
...) is added regardless of the value of n. Also,
The second phase synchronization circuit 8 similarly adds the value -mπ/2 regardless of the value of n.

301 to 309 in FIG. 3 in the first phase-locked circuit 7
The value obtained by adding mπ/2 to the value of is 40 in Figure 4.
1 to 409, and the value obtained by adding -mπ/2 to the values 301 to 309 in Fig. 3 in the second phase locked circuit 8 is the value 411 to 419 in Fig. 4. It becomes like this.

Now, the signal ψ expressed by equation (3). When mπ/2 is added to , it becomes as shown in equation (4).

(0=-Ding・O・Ding・π) Here, when afi-1, equation (4) is expressed as follows. Therefore, if it is determined whether an is 1 or -1, ψ in equation (5). Modulo with respect to π for
) condition ψ shown in Eq. −ψ. −0zQ −(6)ψ. Ya, -
ψ. This can be done by checking whether zQ - (7) is satisfied. In FIG. 2, one sample delay circuits 23, 24 and subtracters 25.
26 and judgment, if the conversion tail is taken in the first phase-locked circuit 7, ψkou,=MOdulOπ(π(an+,-1)−±
-)T2, which is input from the first phase synchronization circuit 7 to the phase error calculation circuit 9.

On the other hand, the signal is similarly input from the second phase synchronization circuit 8 to the phase error calculation circuit 9.

In the phase error calculation circuit 9, Moduloπ/2(ψkout −ψkout
) and a phase error signal is output.

The above will be explained using FIGS. 5 and 6. FIG. 5 shows the values obtained by taking the modulo of π with respect to the values 401 to 409 and 411 to 419 in FIG. Here, in the first phase locked circuit, al, -
1, the sampled values of the output of the delay circuit 25 are detected by the switch 28 in FIG. 2, that is, the values indicated by 501 to 509 in FIG.
The output of switch 28 is fed back to subtracter 21 through loop filter 29 and cumulative adder 30 so that this value becomes zero. Note that in the loop filter 29, the switch 2
The modulo of the output of 8 is taken, noise contained in this output is removed, and the result is supplied to an accumulative adder 30 constituting a digital VCO. On the other hand, in the second phase synchronized circuit 8, a
When the value is -1, the sampled values, ie, the values shown at 511 to 519 in FIG. 5, are detected, and control is performed so that these values become zero. As a result, the first
and the output of the second phase synchronized circuit 7.8 is
The values shown in the sixth factor 601-609 and 611-619 are obtained corresponding to 01-509 and 511-519.

The output signal of the first phase synchronization circuit 7 may be taken out from the output of the subtracter 21 shown in FIG. 2, for example.

The configuration of the second phase-locked circuit 8 is also exactly the same as that of the first phase-locked circuit 7 shown in FIG.
2, the value to be added is simply -mπ/2. Also,
Although the circuit that takes the modulo is not shown in Figure 2, in digital signal processing, the modulo can be realized by ignoring the few bits on the MSB side of the input digital signal, so in reality, all that is needed is to operate the wiring. implemented, and no special hardware is required.

Furthermore, since the first and second phase synchronization circuits 7.8 receive the same signal as input, they operate in exactly the same way once their phase synchronization is established.

Therefore, after synchronization is established, the first and second phase synchronization circuits 7
．． By mutually correcting the internal states of 8, more accurate operation can be achieved. Specifically, for example, a loop filter used in a phase-locked circuit (2 in Fig. 2) is used.
9) If we consider a configuration consisting of coefficient multipliers 71 and 72 as shown in FIG. After synchronization is established, the value corresponds to the carrier frequency offset. That is, the contents of the latch circuits 74 in the loop filters in the first and second phase locked circuits 7 and 8 should be equal after synchronization is established. Therefore, after synchronization is established, by mutually correcting the two so that they are exactly equal, the clock phase error can be detected more accurately. In addition, as a method of mutual correction, there is a method such as taking the average of the contents of two latch circuits and rewriting the result to a new latch circuit. It is also possible to extend this idea and share the cumulative adder itself with both loop filters, in which case the circuit configuration can be roughly simplified.

Other embodiments of the present invention are shown in FIGS. 8 and 9. In both of these embodiments, the circuit scale can be reduced by sharing the 1-sample delay circuit 23.24, the subtracter 25.26, and the determination circuit 27 in the first and second phase-locked circuits 7.8. The parts with the subscript "a" indicate the components of the first phase-locked circuit 7, and the parts with the subscript "a" indicate the components of the second phase-locked circuit 8. .

In the embodiment of FIG. 8, an adder 22a that adds mπ/2
An adder 22b for adding up and -mπ/2 is provided at the downstream stage of the sampling switches 28a and 28b. Note that a 1-sample delay circuit 23' is inserted in the second phase synchronization circuit 8 in correspondence with the 1-sample delay circuit 23.

In the embodiment of FIG. 9, the sampling switch 28a
, 28b are placed after the subtracters 21a, 21b, and these switches 28a, 28b and adders 22a, 22b
One-sample delay circuits 31a and 31b are inserted between the two.

It is clear that the same results as in the embodiment shown in FIG. 1 can be obtained in the embodiments shown in FIGS. 8 and 9 as well. Also, a loop filter 29a.

As mentioned above, it is possible to mutually correct the contents of the latch circuits in the accumulator 29b.

The present invention is not limited to the above-described embodiments; for example, in the embodiments, the input digital modulation signal is an MSK signal, but offset QPSK, TFM
, GMSK, etc., and the present invention is generally effective for modulated signals having two modes. In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of the first phase locked circuit in FIG. 1, and FIGS. 3 to 6 explain the operation of the same embodiment. FIG. 7 is a diagram showing the configuration of a loop filter, and FIGS. 8 and 9 are diagrams showing the configuration of main parts of other embodiments of the present invention. 1.2... Input terminal for digital modulation signals having orthogonal phase relationship, 3, 4... A/D converter, 5... Conversion table, 6... Phase error detection circuit, 7.8.・First
and second phase locked circuit, 9... phase error calculation circuit, 10... phase error signal, 11... loop filter, 12... D/A converter, 13... voltage controlled oscillator, 21.21a, 21b, 25.26--Subtractor, 2
2.22a, 22b...adder, 23, 24°23'
, 31 a, 31 b-1 sample delay circuit, 27.
... Judgment circuit, 28.28a, 28b... Sampling switch, 29.29a, 29b... Loop filter, 30.30a, 30b... Accumulation adder. Applicant's agent Patent attorney Takehiko Suzue Figure 4 Figure 6 Figure 7

Claims (2)

[Claims] (1) Inputs a pair of digital signal sequences in a quadrature phase relationship obtained by sampling a digital modulation signal using a reproduced clock, and corresponds to a combination of digital values representing the amplitudes of these pair of digital signal sequences at each time. a conversion means for outputting the phase information as a digital signal; and a conversion means for receiving the phase information output from the conversion means,
a first phase synchronization circuit that synchronizes with a first phase change component depending on a first transmission data pattern in the digital modulation signal; a second phase synchronized circuit whose period is determined by a second phase change component depending on the transmitted data pattern; A phase error detection circuit comprising: a phase error calculation circuit that calculates a phase error. (2) The phase error detection circuit according to claim 1, wherein the conversion means is a ROM table.