JPS61272941A - 半導体基板の結合方法 - Google Patents

半導体基板の結合方法

Info

Publication number
JPS61272941A
JPS61272941A JP60114220A JP11422085A JPS61272941A JP S61272941 A JPS61272941 A JP S61272941A JP 60114220 A JP60114220 A JP 60114220A JP 11422085 A JP11422085 A JP 11422085A JP S61272941 A JPS61272941 A JP S61272941A
Authority
JP
Japan
Prior art keywords
substrate
holes
photoresist
different kind
semiconductor substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60114220A
Other languages
English (en)
Inventor
Tsutomu Uemoto
勉 上本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60114220A priority Critical patent/JPS61272941A/ja
Publication of JPS61272941A publication Critical patent/JPS61272941A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は集積回路における２種類の半導体基板の結合方
法に関する。
〔発明の技術的背景とその問題点〕
集積回路を多機能化する上において、異種基板を結合す
る配線の数を増せないことが問題となる。
第６図は従来の金線又はアルミニウム線のポンディング
による接続する方法であるが、ポンディングを行える所
が限られ、また線の交差による線１４の短絡の可能性が
あるため、多くの配線は行えなかった。
第７図は従来のＩｎ柱による異種基板の接続である。該
接続法においては、接続する基板の線膨張係数が異る場
合、熱膨張によすＩｎ柱が切断する場合があった。熱膨
張によるＩｎ柱の切断を防ぐ方法としてはＩｎ柱の高さ
を高くする方法が取られていたが、Ｉｎ柱を高く、歩留
りよく作製するためには、Ｉｎ柱の径を小さくすること
ができず、集積式が小さくなるという欠点があった。
〔発明の目的〕
本発明は上述した従来法の欠点を改良したもので高密度
に異種半導体基板を接続し、熱膨張による断線をなくす
ることを目的としたものである。
〔発明の概要〕
本発明は接続したい２種類の半導体基板の線膨張率の間
の線膨張率を有する絶縁体基板に、該基板を貫通する電
気配線を施し、この絶縁体基板によって２種類の半導体
基板を和で結合することを特徴とするものである。
〔発明の効果〕
本発明により、線膨張係数の異なる半導体基板間を電気
的に高密度に接続することが可能となり、温度による半
導体間の電気的に切断されることがなくなった。
また、絶縁体基板に和の電極及び配線を行ったものは半
導体基板部分と別に作製できるため、半導体素子の作製
１日数の短縮を行うことができた。
〔発明の実施例〕
第１図に本発明を用い、シリコン基板上に形成したスイ
ッチ素子のアレーとＩｎＰ７オトダイオードアレーをチ
ッ化シリコン基板にＩｎ電極を形成して貼り合わせたも
のの断面図を示す。
第２図にチッ化シリコン基板を反応性イオンエツチング
で孔をあけた後、該基板に無電解メッキ法に銅薄膜２１
を形成した所を示す。該チッ化シリコン基板上に第３図
に示す様に７オトレジスト３１を塗布し、選択露光によ
り孔の部分のみ該フォトレジストを除去する。該基板を
、電解メッキを行いＩｎを７オトレジストの被着してい
ない部分にＩｎをメッキする。第４図に示す様に孔がＩ
ｎでふさがれ、孔の両端にＩｎが被着した所で、メッキ
を止め、フォトレジスト３１を除去し、銅２１をエツチ
ングして取し除く。第５図にＩｎ電極の形成されたチッ
化シリコン基板の断面図を示す。該基板と、Ｓｉ基板を
位置合わせをして、貼り合わせた後ＩｎＰ基板を貼り合
わせ、第１図の構造の素子を作製した。
従来のＩｎ柱においては　柱の径を３０μｍ以下にする
ことは困難であるが、本発明を用いることにより可能と
なった。また作製した半導体素子は、従来の素子では断
線しやすかった液体チッ素温度と、空温との間の温度変
化にも耐えられた。
〔発明の他の実施例〕
上記実施例で示したｈの電極形成の絶縁体基板は、１枚
だけでなく、２枚以上重ねることも可能である。
また、ＩｎＰとｆ９ｉ　Ｏ組み合わせ以外、Ｉｎ　８ｂ
とＳｉ。
ＨｔＣｄＴ４　と８ｉ等異種半導体間のすべてのものに
本発明は使用可能である。
また、Ｉｎ柱は電界メッキだけでなく、溶融させたＩｎ
に浸すことによりでも形成できる。
【図面の簡単な説明】
第１図は本発明を用いてＩｎＰダイオードアレーと８ｉ
スイツチ素子を電気的に結合させた図、第２図はチッ化
シリコン基板に孔をあけ銅を無電解メッキした図、第３
図は該基板に７オトレジスト膜を被った図、第４図は該
基板にＩｎを電解メッキ法により形成させた図、第５図
は該基板より、フォトレジストを除去し、銅をエツチン
グした図、第６図は従来のリード線のボンディングによ
ル、異種半導体の接続の図、第７図は従来のＩｎ柱によ
る異稽半導体の接続図である。１１：ＩｎＰダイオード
アレー基板、１２：チッ化シリコン基板、１３：シリコ
ンスイッチング奏子基板＋１４：Ｉｎ電極、２１　：Ｃ
ｕ無電解メッキ膜、３１：フォトレジスト、４１：イン
ジウムメッキ層、６１：ｓｔ基板、６２：化合物半導体
基板、６３：金リード線、６４：ポンディングパッド、
７１：Ｉｎ柱。 第１図 第２図 第８図 第４図

Claims (1)

    【特許請求の範囲】
  1. 線膨張係数の異なる２枚の半導体基板を、該２枚の半導
    体基板の線膨張係数の間にある絶縁体基板を介して電気
    的に結合させる際、前記絶縁体基板の表面と裏面を貫通
    する孔をあけ、該孔を金属で埋め込み、該金属の両端に
    インジウムを被着して結合させることを特徴とする半導
    体基板の結合方法。
JP60114220A 1985-05-29 1985-05-29 半導体基板の結合方法 Pending JPS61272941A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60114220A JPS61272941A (ja) 1985-05-29 1985-05-29 半導体基板の結合方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60114220A JPS61272941A (ja) 1985-05-29 1985-05-29 半導体基板の結合方法

Publications (1)

Publication Number Publication Date
JPS61272941A true JPS61272941A (ja) 1986-12-03

Family

ID=14632232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60114220A Pending JPS61272941A (ja) 1985-05-29 1985-05-29 半導体基板の結合方法

Country Status (1)

Country Link
JP (1) JPS61272941A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63246837A (ja) * 1987-04-02 1988-10-13 Canon Inc 電気回路部材
US5323535A (en) * 1991-02-25 1994-06-28 Canon Kabushiki Kaisha Electrical connecting member and method of manufacturing the same
US5379515A (en) * 1989-12-11 1995-01-10 Canon Kabushiki Kaisha Process for preparing electrical connecting member

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63246837A (ja) * 1987-04-02 1988-10-13 Canon Inc 電気回路部材
US5379515A (en) * 1989-12-11 1995-01-10 Canon Kabushiki Kaisha Process for preparing electrical connecting member
US5323535A (en) * 1991-02-25 1994-06-28 Canon Kabushiki Kaisha Electrical connecting member and method of manufacturing the same

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