JPS61267812A - Timing signal generator - Google Patents

Abstract

PURPOSE:To vary the reading cycle of a ROM by securing such a system where the frequency of the clock signal of a counter is varied and a selection circuit selects the ROM in response to the varied frequency of the clock signal to select the address of the ROM. CONSTITUTION:A timing signal generator consists of a binary counter 2, a latch circuit 4, a clock generator 5, a multiplexer 6, (n) pieces of ROM 7 and an interface circuit 8 serving as a selection circuit. Then the information which indicates a specific ROM 7 and a specific clock and decides whether the counter 2 is reset or not is sent to the circuit 8 from a CPU for production of a certain timing signal. Thus the frequencies of the clocks supplied to the counter 2 and the circuit 4 are varied by the output (selection signal) of the circuit 8. Then the ROM 7 having its reading cycle corresponding to said varied frequency is selected to produce a timing signal having a variable cycle with which the signal level is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a timing signal generation device that generates a timing signal using timing sequences stored in a plurality of ROMs.

2. Description of the Related Art A conventional timing signal generator is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-231624. FIG. 2 shows a configuration diagram of this conventional timing signal generation circuit, and numeral 1 denotes a clock signal generator that sends out a clock signal of a constant frequency. 2 is a binary counter. 3
is a ROM which is a read-only memory. 4 is a latch circuit controlled by the clock signal of the clock signal generator 1; The operation will be explained below.

When a clock is input from the clock signal generator 1 to the binary counter 2, the binary counter 2 sequentially counts the clock signal and inputs the count value to the ROM 3 sequentially. Then, the ROM 3 sequentially reads high-level or low-level data corresponding to the address indicated by the count value, and outputs the data from the output terminal 01 as a timing signal. When the count value matches the final address of the timing series, a reset signal is applied to the reset terminal R of the binary counter 2 from the output terminal 00 of the ROM 3, and the binary counter 2 starts counting from 0 again. Therefore, the ROM 3 outputs a continuous timing signal from the output terminal 01. The latch circuit 4 synchronizes the timing signal output from the output terminal o1 with the clock signal and outputs it from the output terminal Q.

Problems to be Solved by the Invention However, in the above configuration, since the clock signal generator 1 only generates a clock signal of a constant frequency, the latch circuit 4 is configured such that the level of the signal changes only at a constant period. However, there is a problem in that only timing signals that do not occur can be output. In view of this, an object of the present invention is to provide a timing signal generation device that can generate a timing signal whose signal level changes at a variable cycle.

Means for Solving the Problems The present invention provides a ROM with n (n≧1) non-uniform read cycles and 2! A clock signal generator that outputs n clock signals (m≧1), a multiplexer that outputs one clock signal from the 2m clock signals, and a clock signal generator that outputs one clock signal from the n ROMs. R.O.
a selection circuit that selects M and outputs a selection signal for selecting one clock signal from the 2m clock signals of the multiplexer; and a selection circuit that counts the clock signal that is the output of the multiplexer, and The timing signal generating device includes a counter that selects the addresses of the n ROMs based on the output.

Operation The present invention has the above-described configuration, and changes the frequency of the clock signal counted by the counter, and the selection circuit selects the ROM according to the frequency, and selects the address of the ROM, thereby changing the pROM address. A timing signal is generated in which the read cycle can be made variable and the cycle in which the signal level changes is variable.

Embodiment FIG. 1 shows a configuration diagram of a timing signal generator according to an embodiment of the present invention. In Figure 1, 2
is a binary counter, 4 is a latch circuit, 6 is a 2° line (m≧1
), 6 is a multiplexer, 7 is n ROMs (n≧1) with non-uniform read cycles, a is not shown, but a data line is connected to the computer's CPU. This is an interface circuit that serves as a selection circuit connected via. The operation of the timing signal generating device of this embodiment configured as described above will be described below. Although not shown, C
PU, in order to generate a certain timing signal, n
Information such as which ROM to select from among the ROMy, which clock to select from the 2° clocks generated from the rip-pock generator 5, and whether to reset the binary counter 2 is transmitted via the data line. When sent to the interface circuit 8, the interface circuit 8
In order to select n ROMs from ROM1 to ROM n, n chip select signals C81 to C
Make one signal of 9n 7 tape high. At the same time, the multiplexer 6 selects one of the 2m clocks generated by the clock generator 5.
The interface circuit 8 outputs a book selection signal. The multiplexer then outputs the selected clock signal to the binary counter 2 as a count clock. The binary counter 2 sequentially counts the clock signals inputted to the multiplexer, and sequentially converts this count value to n.
input into the ROM 7.

Of the n ROMs 7, the interface circuit 8
The RO selected by the chip select signal which is the output of
M sequentially reads high-level or low-level data corresponding to the address indicated by the count value, and outputs it from the output terminal 01 as a timing signal. and,
When the count value matches the final address of the timing series, a reset signal is applied to the reset terminal R of the binary counter 2 from the output terminal oO of the selected ROM 7, and the binary counter 2 is reset from 0 again. Start counting. Further, when the reset signal outputted from the interface circuit 8 becomes active high, the binary counter 2 is forcibly reset and starts counting from 0. The latch circuit 4 synchronizes the timing signal output from the output terminal 01 with the clock signal selected by the multiplexer 6 and outputs it from the output terminal Q.

As described above, according to this embodiment, the frequency of the clock input to the binary counter 2 and the latch circuit 4 can be made variable by the selection signal output from the interface circuit 8, and the frequency of the clock can be varied by the selection signal output from the interface circuit 8. By selecting a ROM with a corresponding read cycle, it is possible to generate a timing signal in which the period in which the signal level changes is variable. In addition, in the embodiment, the binary counter 2 was used as a counter to generate the address of the ROM 7, but
Other types of counters may be used to change the way of addressing.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, it is possible to generate a timing signal whose signal level changes at a variable period, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a timing signal generation device that generates a timing signal using a ROM in an embodiment of the present invention, and FIG. 2 is a configuration diagram of a timing signal generation device that generates a timing signal using a conventionally known ROM. It is a diagram. 2...Binary counter, 4...Latch circuit, 6...Clock generator, 6...Multiplexer, 7...n pieces OROM, 8・
...Interface circuit.

Claims (1)

[Claims] n ROMs (n≧1) that store timing sequences consisting of arrays of high-level data and low-level data with uneven read cycle times and 2^m ROMs with different frequencies.
a clock signal generator that sends out clock signals (m≧1); a multiplexer that uses the two clock signals as input signals and outputs one clock signal; a selection circuit that selects a ROM and outputs a selection signal for selecting one clock signal from among the 2^m clock signals of the multiplexer; and a selection circuit that counts the clock signal that is the output of the multiplexer; By this count output, the n
1. A timing signal generating device comprising: a counter for selecting an address of a ROM.