JPH05297070A - Ic testing apparatus - Google Patents

Abstract

PURPOSE:To obtain an IC testing apparatus wherein it can reduce the scale of a pattern generator and it can generate various kinds of generation timings of a pattern signal. CONSTITUTION:Timing set data is storing in a timing sequence memory 19 which is separated from a pattern data memory 11B. When the repetition of the same pattern exists, its repetition number N is read out from a control table memory 11A and the repetition number N is set in a variable frequency divider 17. A rate clock is given to the variable frequency divider 17 from a rate generator 12; the rate clock is frequency-divided to 1/N; the control table memory 11A and the pattern data memory 11B which are to be read out next by its frequency-division output are accessed; pattern data which is to be generated next and its repetition number N are read out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for testing a semiconductor integrated circuit (hereinafter referred to as IC).

[0002]

2. Description of the Related Art FIG. 3 shows a schematic configuration of a conventional IC test apparatus. Reference numeral 11 in the figure denotes a pattern generator. The pattern generator 11 is composed of a control table memory 11A and a pattern data memory 11B. The pattern data memory 11B outputs pattern data Pa and Pb each time the rate clock output from the rate generator 12 is input to the pattern generator 11. The pattern data Pa is given to the waveform formatter 14. A timing clock Ta is applied from the clock generator 13 to the waveform formatter 14, and a pattern signal having rising and falling edges and timings thereof is generated by the timing clock Ta and the pattern data. This pattern signal is given to the IC 16 under test through the driver DR group.

The response output signal of the IC 16 under test is judged by the voltage comparator group CP to have a normal logic level, and the judgment result is inputted to the logic comparator 15. The logical comparator 15 reads the logical value of the response output of the IC 16 under test at the timing of the clock Tb supplied from the clock generator 13, and the logical value and the pattern generator 1 are read.
The expected value pattern data Pb given from 1 is compared, the occurrence of mismatch is detected, and the defective portion of the IC 16 under test is determined.

As described above, the conventional IC test apparatus uses the timing clock Ta output from the clock generator 13.
The phase (1) defines the timing (phase) of rising and falling of the pattern signal given to the IC under test 16 and the timing of reading the logical value of the logical comparator 15. The operation of the waveform formatter 14 will be described with reference to FIG. Figure 4
A indicates a clock that defines a test cycle. This clock defines the test cycle. FIG. 4B shows pattern data output from the pattern generator 11. 4C and 4D show the timing clock Ta supplied from the clock generator 13 to the waveform formatter 14. This timing clock Ta is a two-phase clock AT
a and BTa. Waveform formatter 1
In this example, 4 shows the case of operating in a mode for generating an RZ waveform (return zero waveform). That is, clock A
The rising edge of the waveform is defined by Ta, and the falling edge of the waveform is defined by the clock BTa. When the pattern data is "1", the pattern waveform given to the IC 16 under test rises to "1" logic and falls at the clock BTa. When the pattern data is "0", no pattern waveform is generated even if the clock ATa is given.

Here, the clocks ATa and BTa are given delay times t ₁ , t ₂ , t _3, ... In each test cycle,
The delay times t ₁ , t ₂ , t ₃ ... Are controlled to generate a pattern waveform at an arbitrary phase position in each test cycle. The delay times t ₁ , t ₂ , t _3, ... Are controlled by the phase control data given from the rate generator 12 and the timing set data outputted from the control table memory 11A provided in the pattern generator 11.

The control table memory 11A and the pattern data memory 11B are accessed by a common address. At each address, pattern data of a pattern signal given to each terminal of the IC under test 16 and a delay time for defining a rising timing and a falling timing of a logical waveform determined by the pattern data are stored as a set. ..

The pattern data is the pattern data memory 1
1B is supplied to the waveform formatter 14 and the logical comparator 15. Timing set data defining the delay time of the pattern signal supplied to each terminal is read from the control table memory 11A and the rate generator 1 is supplied.
Given to 2. In the rate generator 12, the timing set data for all terminals is converted into phase control data corresponding to the delay time, and this phase control data is converted into the clock generator 13.
To generate timing clocks ATa and BTa.

A rate clock is output every time the phase generator 12 outputs the phase control data, and the rate clock is supplied to the control table memory 11A. The control table memory 11A is provided with the rate clock to calculate the address to be accessed next by calculation from the previously read data, and accesses the address to read the pattern data and the timing set data. By repeating this, the generation of the pattern signal and the expected value pattern signal is continued.

[0009]

The pattern generator 11 calculates the address to be accessed next each time the rate generator 12 outputs the phase control data, and repeats the operation of reading the timing set data and the pattern data. .. As a result, even when the pattern data is not changed and only the phase control data is sequentially changed, the control table memory 11
It is necessary to store a combination of each timing set data and pattern data in A and the pattern data memory 11B. For this purpose, the control table and memory 11
A and the pattern data memory 11B have a drawback that the memory capacity constituting the memory becomes large.

Further, if an attempt is made to select various combinations of timing set data and pattern data, each timing set data and pattern data combination must be stored in the memory. There is an inconvenience that the capacities of the table memory 11A and the pattern data memory 11B become large.

An object of the present invention is to reduce the memory capacity of the control table memory 11A and the pattern data memory 11B, and to select a wide variety of combinations of pattern data and timing data. Is to provide.

[0012]

According to the present invention, the timing set data is stored in the timing sequence memory provided separately from the control table memory 11A, and the control table memory 11A stores the number of times of repeating the same pattern. Further, when the number of repetitions N of the same pattern is read, a variable frequency divider is provided which operates with the number of repetitions N as a frequency division ratio. The variable frequency divider divides the rate clock output from the rate generator and supplies it to the pattern generator 11. A rate clock is directly applied to the timing sequence memory.

Therefore, according to the present invention, the timing set data is read from the timing sequence memory in a one-to-one correspondence in synchronization with the rate clock. On the other hand, when the same pattern is continuously generated, the number of consecutive times N is set in the frequency divider. As a result, the frequency divider divides the rate clock by 1 / N and supplies it to the pattern generator. Therefore, the pattern generator continues to output the same pattern while N rate clocks are output. During this period, the timing sequence memory can output N pieces of arbitrary timing set data in synchronization with the rate clock.

[0014]

FIG. 1 shows an embodiment of the present invention. In FIG. 1, portions corresponding to those in FIG. 3 are designated by the same reference numerals. In the present invention, the rate generator 12 and the pattern generator 1
A variable frequency divider 17 is provided between the variable frequency divider 17 and 1. This variable frequency divider 1
7 can be constituted by a preset counter, for example. The preset terminal P is given the number of times N of repetition of the same pattern from the control table memory 11A. The number N of repetitions of the same pattern is given to the preset terminal P, the value of N is preset, and the variable frequency divider 17 operates as a 1 / N frequency divider (N-ary counter).

A 1-bit rate clock included in the phase control data output from the rate generator 12 is applied to the clock input terminal CK of the variable frequency divider 17. This rate clock is counted, the next number N of times of repeating the same pattern is taken in at the (N + 1) th time, and the value of N is preset. The value of N corresponding to the division ratio is the control table memory 11A.
Read from. That is, the value of the number of repetitions N is stored in the control table memory 11A at the same address as the address where the pattern data for repeatedly outputting the same pattern is stored,
At that time, the address of the timing sequence memory 19 storing the timing set data to be output is stored. The address read from the control table memory 11A is stored in the address counter 18. The rate clock output from the rate generator 12 is applied to the clock input terminal CK of the address counter 18.

The count value of the address counter 18 is given to the timing sequence memory 19 as an address signal. Timing set data is stored in the timing sequence memory 19. The address signal output from the control table memory 11A is stored in the address counter 18, the address signal is supplied to the timing sequence memory 19, and the timing set data stored at the address is read.

The timing set data read from the timing sequence memory 19 is given to the rate generator 12 and the clock generator 13. The rate generator 12 converts the timing set data read from the timing sequence memory 19 into phase control data, and supplies the clock generator 13 with the phase control data. At the same time, the rate clock included in the phase control data is given to the variable frequency divider 17 and the address counter 18.

The clock generator 13 outputs the timing clocks ATa and BTa to the phase positions delayed by a predetermined time from the rate clock according to the phase control data as shown in FIG.
Is output and given to the waveform formatter 14. The address counter 18 increments the address by adding the rate clock to read the timing set data written in the next address of the timing sequence memory 19. This timing set data is the rate generator 1
2 and is converted into phase control data.

In this way, the state of the pattern generator 11 is fixed and does not change until the rate clock is given to the variable frequency divider 17 by the number equal to the value of N given to the variable frequency divider 17. Therefore, the same pattern data is continuously output until the variable frequency divider 17 is supplied with N rate clocks. FIG. 2 shows an example of this operation. The example of FIG. 2 shows the case where N = 4. When the fifth rate clock is applied to the variable frequency divider 17, the variable frequency divider 17 outputs a frequency division signal, and the frequency division signal causes the state of the pattern generator 11 and the frequency division of the variable frequency divider 17 to be performed. The number N is updated. In this updating operation, various data read from the control table memory 11A are calculated in the same manner as in the conventional case, the addresses of the control table memory 11A and the pattern data memory 11B to be accessed next are determined, and the variable frequency divider 17 is determined from the addresses. The frequency division number N and the pattern data given to are read.

[0020]

As described above, according to the present invention, for one pattern data read from the pattern data memory 11B, the timing sequence memory 19 is provided by the number of frequency divisions N given to the variable frequency divider 17. Different timing set data can be read from. This timing set data is stored in the control table memory 11
By predefining N addresses from the address given by A so that the timing changes will be suitable for the test item, it is possible to test all the timings planned by one pattern. As a result, the control table memory 11A and the pattern data memory 11B
Since it is possible to reduce the number of timing control data and pattern data to be prepared, the capacity of the control table memory 11A and the pattern data memory 11B can be reduced.

Further, since the pattern data and the timing set data are read from another memory and combined, the number of combinations of the pattern data and the timing set data can be increased. Therefore, there is an advantage that various combinations of timing set data and pattern data can be obtained without increasing the capacities of the control table memory 11A and the pattern data memory 11B.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the present invention.

FIG. 3 is a block diagram for explaining a conventional technique.

FIG. 4 is a block diagram for explaining the operation of a conventional technique.

[Explanation of symbols]

 11 pattern generator 11A control table memory 11B pattern data memory 12 rate generator 13 clock generator 14 waveform formatter 15 logical comparator 16 IC under test 17 variable frequency divider 18 address counter 19 timing sequence memory

Claims (1)

[Claims] 1. A. Timing set data that defines the rising and falling timings of each pattern signal applied to each terminal of the IC under test from the pattern generator configured by the control table memory and the pattern data memory, and the logical value of the pattern signal. The pattern data is read out, the timing set data is converted into phase control data in the rate generator, this phase control data is given to the clock generator, and this clock generator causes the rising and falling timings of the pattern signal. In an IC test apparatus that generates a clock that specifies the above, supplies the clock to a waveform formatter, generates a pattern signal in the waveform formatter, and applies the pattern signal to the IC under test to test the IC under test. A timing sequence memory which is provided separately from the pattern generator and stores the timing set data; An address for reading the timing set data defining the initial timing of the same pattern read from the control table memory together with the number of repetitions N of the same pattern from the timing sequence memory is stored, and from this address, the rate generator is stored. An address counter that increments the address of the timing sequence memory by counting each time a rate clock is output, and D. The number N of repetitions of the same pattern read out from the control table memory is set to a division ratio of 1 / N, the rate clock is divided, and the divided output is used as the control table memory and pattern data. An IC test apparatus comprising: a variable frequency divider for giving a read address to a memory and updating the read address.