JPS61267360A - Mos static ram circuit - Google Patents

Abstract

PURPOSE:To obtain a static RAM circuit of complete CMOS which is excellent in both area and performance by a construction wherein the high-load wirings are shared by the low-resistance metal wirings by using a multilayer metal wiring process. CONSTITUTION:Metal wirings are constructed on the condition of the use of a CMOS process in which two layers can be utilized, the upper layer metal wiring being used for data lines 28 and grounding lines 29, 29', and the lower layer metal wiring being used for word lines 27 and a power supply line 32 that are othogonal thereto. This is because the connection with the low layer metal wiring can easily become smaller in area because of the connection of the word line polysilicon wirings and the metal wirings, and speeding up is intended by using the upper layer wiring having the least delay time as the data lines. The construction is such that the left and right sides of a memory cell are separated by the grounding lines in order to prevent the unit data line pair from adversely affecting other bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a matrix circuit in a static RAM, and more particularly to a MOS static circuit that can be configured with a rainout suitable for a CMOS process that allows multilayer metal wiring.

[Background of the invention]

4M as a static RAM matrix cell system
There are O8, 5MO8, 6MO8 systems, etc., and each has its advantages and disadvantages. The system targeted by the present invention is the complete cMO3 (6MO8 system), which is effective in low power consumption, noise immunity, and cost reduction of process steps, as described in Nikkei Electronics, March 17, 1980, p. 136.

An example of a complete CMO3 static RAM matrix circuit is shown in FIG. Circuit 1 is a data storage circuit, and data is held by a feedback circuit configuration.

N-channel MOs 82 and 2' are transfer MOs 8) transistors used to supply data from the circuit 1 to the data lines 3 and 3' (read operation) or update data in the circuit 1 (write operation). Line 4 is a word line for controlling transfer MoS transistors 2 and 2' used for read and write operations.

The layout of the RAM matrix circuit is a factor that determines the chip size, so there are various transistor arrangements and configurations. Basically, the layout configuration as shown in Figure 2 was realized. 9. The N-channel MOS transistor in FIG. 10 P-channel MOS transistors
The power supply line 7 is a diffusion layer, the word line 5 is a gate material (polysilicon), and the top wiring A1 layer is
It was used for the data line pair 6, 6' and the ground line 8. A vertical sectional view of this is shown in FIG. PMOS transistor 1 formed on n-substrate 19 fixed at power supply level
5. NMOS transistors 16 and 17 formed on the p-substrate 20, which is fixed below the ground level, have drains and sources that match the logic.

and the gate are connected by wiring. MOS transistors 15 and 16 correspond to the data holding circuit 1, and MOS transistor 17 is a transfer MOS used for inputting and outputting data to and from the data line.
It corresponds to transistor 2 (or 2'). As shown in Fig. 2, the A1 wiring is formed vertically (corresponding to 11 wirings in Fig. 3).
The drain side 18 of the memory cell array 5 cannot be laid out with metal wiring, so a diffusion layer is used to connect the memory cells, and metal wiring is used at both ends of the memory cell row. Although this is a commonly used method, a drop in the power supply voltage cannot be avoided due to the distribution of the diffused resistance. The word line 14 also serves as the gate electrode of the transfer MOS transistor 17 of the memory cell, and is therefore formed of polysilicon wiring. The delay of a word line made of polysilicon is determined by the product RC of wiring resistance R and wiring capacitance C, so it remains a steady value even if the process is scaled down, and can be compensated for by improving peripheral operating performance. Ta. Due to these inconveniences, it has been difficult for conventional MOS static RAMs to operate at high speeds with large capacity.

In short, methods using polysilicon or diffusion layers as interconnects have large junction capacitance and interconnect capacitance due to the close distance to the substrate, and have poor conductivity and high resistance, making the interconnects unsuitable for high-speed operation. Therefore, traditional complete CMO
In S static RAM, the speed has been increased by changing the shape of the memory cell depending on the application and by making improvements to the peripheral circuitry. However, there is a limit to the speedup that can be achieved with this method, and the emergence of new technology is desired.

[Purpose of the invention]

The purpose of the present invention is to use a CMOS process capable of multilayer metal interconnection to create a complete CMOS device with superior area and performance.
8 (6MO8 system) static RAM circuit.

[Summary of the invention]

In the present invention, by using a multilayer metal wiring process and sharing the conventional high-load wiring with a low-resistance metal wiring, wiring resistance can be significantly reduced.

Furthermore, since metal wiring allows for a greater distance between substrates than diffusion layers or polysilicon, wiring capacitance can also be reduced at the same time.

Another feature of the present invention is that the data line and the ground line are made of top layer metal wiring so as to achieve high-speed control and high stability.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 4, 5, and 6. FIG. 4 is a transistor circuit diagram of a memory cell of a complete CMO8 (6MO8 system) static RAM. Circuit 24 is an nNO3 transistor, circuit 2
5 forms a PMOS transistor. The data on the data line pair 22 can be written through the transfer MOS transistors 23 and 23' in the memory cell, and the data on the data line pair 2 can be
Read data to 2. Line 21 is transfer Mo
The word line 26, which controls the S transistors 23 and 23', is a power supply line that supplies the P channel MOS transistors. FIG. 5 shows an example of a layout configuration using a process assuming two layers of metal wiring, which corresponds to the layout configuration example using the conventional process shown in FIG. Second
The circuits 9 and 10 shown in the figure are laid out as shown in FIG. Word line 6 is 28
．． The ground wire 8°8' is laid out like 29.29'. The present invention is constructed on the assumption that a CMOS process that can use two layers of metal wiring is used; the upper layer metal wiring is used for the data line 28 and the ground line 29, 29', and the lower layer metal wiring is used for this. Word line 27.
It was used for the power supply line 32. This is because the connection between the word line polysilicon wiring and the metal wiring with the lower layer metal wiring is easier and requires less area, and the upper layer metal wiring with the smallest delay time is used as the data line for operation. I'm trying to speed it up.

However, it is also possible to create a memory cell even if the wiring materials are reversed, that is, the upper layer metal wiring is used as a word line and a power supply line, and the lower layer metal wiring is used as a data line and a ground line. Although both wiring configurations are the same, the left and right sides of the memory cell are separated by a ground line so that changes in the unit data line pair do not adversely affect other pins 1 to 1. FIG. 6 shows a cross-sectional configuration when two layers of metal wiring are used. p-channel MO8) on n-substrate 42 - transistor 38. p-substrate 43
The structure of the upper n-channel MOS transistors 39 and 40 is the same as that in FIG. However, lower resistance has been achieved by adding underlying metal wiring to the diffusion layer and polysilicon wiring. The wiring 41 is the power supply line connecting the diffusion layer to the lower metal wiring, and the wiring 37 is the transfer MO
The word line and wiring 33 connecting the gate electrode 36 of the S transistor 40 to the lower layer metal wiring are data lines using upper layer metal wiring.

〔Effect of the invention〕

According to the present invention, by using a process that allows multilayer metal wiring, problems such as voltage drop in power supply lines and increased propagation delay time due to wiring load can be solved, so that large-capacity memory with stable operation can be achieved. This has the effect of making it possible to design a circuit.

[Brief explanation of drawings]

Figure 1 is a memory cell circuit diagram of a complete CMOS static RAM, Figure 2 is a diagram showing the basic layout of the circuit when the circuit in Figure 1 is designed based on the conventional process,
Figure 3 is a vertical cross-sectional view of a memory cell produced by a conventional process.
Figure 4 is a transistor circuit diagram of a memory cell, Figure 5 is a diagram showing the layout method of the present invention, and Figure 6 is a vertical cross-sectional view of a memory cell manufactured by a CMOS process using two-layer metal wiring applied to the present invention. be. 1...Data storage circuit, 2.2', 23.23'.
・Transfer MOS transistor, 3.3', 6.6'
. 33...Data line, 4,5,21,37...Word line, 7.26,32,41...Power line, 8,26,3
2...Grounding wire, 9, 16, 17, 39, 40...=nM
OS transistor, 10,15,38...pMOS transistor, 18...drain of pMO5 transistor, 19°42...n substrate, 20.43...p substrate, 24.25...circuit, 33 ...upper layer metal wiring, 3
6... Gate electrode, 37... Lower layer metal wiring that runs parallel to the word line and short-circuits with the polysilicon of the word line to lower resistance, 41... Lower layer metal for preventing voltage drop in power supply voltage. wiring.

Claims (1)

[Claims] 1. In a memory cell, word lines and power lines are laid out using gate material and lower layer metal wiring, and upper layer metal wiring is laid out in a direction perpendicular to these to form data lines and ground lines. Characteristic MOS static RAM circuit. 2. Regarding the above data lines, unit bit data line pair (
Two data lines d, @d@) that supply positive and negative voltages are separated so that the data is not affected by adjacent bits,
2. The MOS static RAM circuit according to claim 1, wherein inter-substrate capacitance is reduced by using upper layer metal wiring.