JPS61267152A - Error cause displaying system - Google Patents

Abstract

PURPOSE:To decrease the cost by obtaining the OR of the error detected by the hardware and the error detected by the microprogram and displaying it at the register provided in the channel as a channel error. CONSTITUTION:In the channel (CH) controlled by a microprogram (MP) which a processor MPU executes, the error cause is displayed at the special bit of a status register (AST) as a channel error (AERR) by the OR output of the error detected by the hardware and the error bit detected by an MP. When AERR is '1', the error cause held at the work memory in said CH is displayed at the control register. When a CPU to control said CH is executed and AERR is '1', a command is issued, and when the execution is normally completed, the contents of the above-mentioned control register are logged as an MP error. Consequently, the error displaying of AST is finished by one bit only and the exclusive-use displaying register is not necessary.

Description

[Detailed Description of the Invention] [Table of Contents] Overview/Field of Industrial Use Conventional Technology Problems to be Solved by the Invention Means for Solving Problems Action Embodiments Effects of the Invention [Overview] Processor (MPU) In the channel (CH) controlled by the microprogram executed by the microprogram, the channel error (
When the above microprogram is started, the channel error (AIERR) is displayed as "
1”, the cause of the error held in the work memory in the channel (CH) is displayed in the control register, and the central processing unit (
When the input/output processing program executed in the CPU is started, the above channel error (AER[l)
1", when a NOP command is issued and ends normally, the contents of the above control register are logged as a software error, and when the NOP command does not end normally (and times out), the hardware This is to be recognized as an error.

[Industrial application field]

The present invention relates to a method for distinguishing and displaying error causes detected by a microprogram and hardware detected in a channel (CH) controlled by a microprogram executed by a processor (MPU).

With the recent remarkable progress in semiconductor technology, the logic circuits that make up computer systems are becoming more highly integrated.If the logic circuits require higher speeds, highly integrated logic elements are required. Since the amount of heat generated from the device increases, there is a limit to the degree of integration, and the current situation is that it is not possible to increase the degree of integration too much.

On the other hand, as computer systems go online, and as the reliability of each logic circuit is required to be improved, means for displaying the cause of a failure are becoming increasingly detailed.

Due to these circumstances, the input/output device (Ilo) and main memory bag;
A channel (
Regarding the error cause display method in CH"), there has been a need for a method that can display error causes in detail without increasing the hardware as much as possible.

[Conventional technology]

When displaying the error causes detected by the microprogram and the error causes detected by the hardware in a channel (CH) using a processor, for example, a microprocessor, conventionally, ■Channel control that the channel (CH) has Should the status register (AST) (register for command completion information) be provided with a bit corresponding to each error?

(2) Only a representative error display bit is provided in the status register, and its details are displayed using display bits separate from the status register.

Figure 4 is a diagram showing an example of a conventional error cause display method, in which the channel (Cl) status register (AST)
In this example, errors detected by the microprogram and hardware errors are displayed separately, and the details of the microprogram error are provided in the error cause display register. This is what is shown.

The reason why detailed error display is limited to microprogram errors in the above display method is because there are generally fewer types of hardware errors, but there are many types of errors detected by software such as diagnostic programs. by.

[Problem that the invention seeks to solve]

Therefore, in the conventional method, since multiple bits are required to display the cause of an error, it takes time to check the content of the error with software, and the microprogram for checking is complicated. Therefore, there was a problem that the memory capacity increased and the cost became high.

In method (2), microprogram errors/hardware errors are displayed in a 1-bit status register, so the time required to search for errors is shortened, but
There is a problem in that a separate register is required for displaying details, which increases costs.

In view of the above-mentioned conventional drawbacks, the present invention provides a method for detecting microprograms with many types of errors, by quickly identifying microprogram errors/hardware errors, and without increasing the amount of hardware for displaying error causes. The purpose of this invention is to provide a method that enables detailed display of the cause of an error.

[Means for solving problems]

FIG. 1 is a diagram showing the configuration of an error cause display method according to the present invention.

As mentioned above, there are generally few types of hardware errors, so they do not require detailed display, but for microprogram detection errors, for example, depending on the configuration of the diagnostic program, there may be many types of errors (therefore, it may be necessary to 1) Errors detected by hardware and errors detected by, for example, a diagnostic microprogram or a command execution program. are logically summed as shown in figure (a), and a channel error (
AERR), but details of the cause of the error are not displayed at this point.

2) For errors detected by the microprogram, as shown in (b), the detailed cause is displayed in the existing control register at the next microprogram startup.

[Effect]

That is, according to the present invention, a channel (C
In H), the logical sum output of the error detected by the hardware and the error bit detected by the above microprogram is displayed as a channel error (AERR) in a specific bit of the status register (AST), and the above microprogram is started. When the channel error (AERR) is 1", the cause of the error held in the work memory in the channel (CH) is displayed in the control register, and the central control unit controlling the channel (CH) When the input/output processing program executed in the processing unit (CPU) is started, the above channel error (A
ERR) is '1', issue a NOP command, and when it completes normally, log the contents of the control register above as a microprogram error,
When the NOP command does not complete normally and times out, it is recognized as a hardware error, so the error display in the status register (AST) only needs to be 1 bit, speeding up error detection. At the same time, the detailed cause required when a microprogram detection error occurs is displayed in the existing control register, which eliminates the need for a dedicated display register, resulting in a significant cost reduction.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a diagram showing the configuration of a computer system to which the present invention is applied, and FIG. 3 is a flow chart showing means for displaying and recognizing error causes by implementing the present invention. The error cause display method inside the channel (CH) is shown in (b)
) indicates a method for recognizing the cause of an error by software, and the same reference numerals indicate the same objects throughout the figures.

In the computer system shown in FIG.
The microprogram (referred to as 3) stored in 33
In order to reduce the amount of hardware, a device control register (hereinafter referred to as OCR) and a startup (command) are stored in the random access memory (hereinafter referred to as RAM) 34 in the channel (CH) 3. A central processing unit (hereinafter referred to as
The interface with the CPU 1 is configured such that a channel control register (hereinafter referred to as ACR) 31 is shared by a plurality of input/output devices (Ilo) 4.

In this channel control method, input/output devices (Ilo
) A command for channel (CH) 4 is divided into a channel command for channel (CH) 3 and a device command for device (Ilo) 4. The channel command is issued by CPU 1, and the device command is issued by CPU 1 based on the channel command. (CH) 3 can be obtained by reading from the main memory (MM) 2.

In addition, the ACR 31 includes a register (DV^) that specifies the device at the time of channel startup, a register (AOP) that specifies the type of channel command, a register 1 that displays the status at the end of the command, and the status register (hereinafter referred to as AST). ), a register (IDVA) that displays 5 interrupt devices, and a control register, and one channel control information is stored at a time, and its contents are
Until it is saved in the OCR of AM 34, the above A
The channel busy (hereinafter referred to as ABSY) bit of ST is set to "1", and reception of the next channel command on the channel (CH) 3 is inhibited.

The operation of displaying the cause of an error by implementing the present invention in such channel (CH) 3 will be described below.

First, cpυ1 executes the input/output processing program, reads ACR31 (7) AST provided as the only CPU interface, and if ABSY is not "1 degree", the device address (DVA) and the channel are read. By writing a command (AOP) to the AC!231, the channel (CH) 3 can be activated.

The channel (CH) 3 becomes A when the activation is applied.
After setting ABSY in AST in CR31 to “1”,
The channel command is saved in the DCR on the RAM 34 and input into the command queue.

When the input of the channel command to the queue is completed, the ABSY is set to 0' and the CPU 1 functions to be able to receive a new channel command.

When the channel commands input into the command queue are sequentially read out from the command queue by the command execution program started by the monitor in the channel (CH) 3, the machine number of the corresponding input/output device (Ilo) is read out. The corresponding OCR is referenced and the corresponding DCI? The above device command is retrieved from the specific area of the main storage device (1'1M) indicated by and the input/output processing instructed by the device command is executed.

When the execution of the device command is completed, it is placed in an interrupt queue on the RAM 34, and the input/output process is retrieved again by the command execution program.
By making a final interrupt to CPU 1,
A series of input/output processing is completed.

Therefore, in ABSY 1, the channel command issued by the input/output processing program executed by CPU 1 is written to ACR 31 in channel (CH) 3, and then input to the command queue in RAM 34. This indicates the period until the

The activation of the input/output processing program executed by the CPU 1 means the activation of software to be described later, and the activation of the software issues a channel command, which is provided as a CPU interface for channel (CH) 3. The microprogram operation activated when written to the ACR 31 described above corresponds to the channel command activation described later.

The cause display and recognition method for various errors that occurred in the channel (CH) 3 started in this way are explained in the first section.
This will be explained with reference to FIGS.

In the present invention, as explained in FIG. 1, the details of the cause of the error are displayed in the existing control register (register for command activation information) in channel (CH) 3. At the time when the error occurs, it is necessary to prevent a collision between a hardware error and a microprogram error.

Specifically, when an error occurs, the cause of the error is not displayed in the control register, but the AST channel error (hereinafter referred to as AEl?R) bit in the ACR31 is simply ORed. Only cents will be given depending on the condition.

Therefore, when AERR = 1, the function identifies whether it is a hardware error or a microprogram detection error, and only when it is recognized as a microprogram detection error, the detailed cause is stored in the control register and logged. The main focus of the present invention is on the means for making this happen.

First, in FIG. 3, (a) shows the result when CPU 1 executes an input/output processing program (i.e., software) and issues a channel command, and channel ((:)i) 3 is activated. This shows an error cause display means in channel (CH) 3, and the above-mentioned BSY bit is set to 1.

Step 40: Check whether AERR=1, and if it is '1', move on to the next Ste/knob 41, but if not, jump to step 46.

Step 41: Before the channel command currently being processed,
The detailed cause of a microprogram (diagnosis program or command execution program) detection error that occurs when executing a channel command issued by the CPU 1 and is stored in a specific area of the RAM 34, for example, is coded in a control register. Set and display.

Step 42: Set ABSY to "0" and wait for the next channel command.

Step 43: Execute the self-diagnosis program stored in the CS 33 of channel (CH) 3 or the above-mentioned command execution program.

The command execution programmer 11 sequentially takes out the channel commands input into the command queue, and
The device command is read from the area of the main memory (MM) 2 indicated by the command, and the input/output device (device: Jlo) 4 is accessed according to the contents of the device command.

Step 44: During the execution of the microprogram, it is determined whether or not the microprogram detection error has occurred. If the error has occurred, the process jumps to step 45, but if the error has not occurred, it is determined whether or not the microprogram detection error has occurred. Returning to step 43, the execution of the microprogram continues.

Step 45: The error set circuit shown in FIG. 1(a) simply sets the AERR bit of AST to 1, but does not display the cause of the error.

Step 46: Channel (CH) 3 is activated and A
Since ERR is 0, the channel command is executed. Specifically, the channel command is stored in the RAM 34.
The command is saved to the OCR and placed in the command queue.

By performing error cause display control as described above,
When an error occurs, regardless of whether the error is a hardware error or a microprogram detection error, the ΔERR bit is simply set to °l° under the logical sum condition of the two, and at that time, the RAM The detailed cause stored in the specific area of 34 is set in the control register when the next channel is activated, so there is no possibility of a conflict between a hardware error and a microprogram detection error. There is a characteristic called.

Next, the error cause H128fJt method performed at the time of startup of the input/output processing program executed by the CPU 1 will be explained with reference to FIG. 3(b).

Step 50: Channel (CH) from CPU 1
3, the previous channel command or termination interrupt information is stored in the ACR 31 until the next channel command is issued or there is a termination interrupt from the input/output device (Ilo) 4. Therefore, the corresponding ACR
Take out the ABSY bi-nod from the AST of 31 and set it to “1”.
``We'll see if that's the case.

If the ABSY bit is “1”, the channel (C1l) 3 is activated before the channel (C1l) 3 is activated.
Since the channel command sent to CH) 3 is in the process of being input to the command queue, step 55 is executed.
Jumps to and loops between step 50, but f, A
If the BSY bit is not "1", the process moves to step 51 because the channel command has been input into the command queue.

Therefore, even when ^BSY=1, channel (C)I
) If 3 is normal, ABSY=0 eventually,
You can proceed to step 51.

Step 51: AST AI! Check whether the RR bit is "1" and if it is "1", proceed to the next step 52 to identify whether it is a hardware error or a microprogram detection error, but if ABRR is 0, it is normal. Since this is an action, the process jumps to step 57.

Step 52: CPU 1 issues a NOP command and moves to the next step. Usually, here, ABSY・1
becomes.

Step 53: Check whether ABSY is 1. If it is 1, it loops with step 56 and the corresponding N
Wait for the OP command to be submitted to the command queue.

Then, when ABSY-0 is reached, the process moves to step 54.

Step 54: Since the above NOP command was successfully submitted to the command queue, the 1HR detected in step 51
R = 1 is not a hardware error, but is recognized as a microprogram detection error that occurred during the execution of the previous channel command, and the contents of the control register stored in step 41 above, that is, the details of the microprogram detection error. Log the cause and make it possible to analyze its contents.

Step 55 Step 50 and Roof 8E
Check whether it is RR・l. If AERR=1 is detected during the loop period, it means that an error has occurred while ABSY=1, but while ABSY=1, the channel command issued by CPU 1 is It is recognized as a hardware error since the actual device command has not yet been executed until it is submitted to the command queue.

However, if Δ[ERR=O, the process returns to step 50 and waits in a loop until the command is eventually input to the command queue.

Step 56: Detecting a timeout after executing the NOP command means that the NOP command was not executed normally, so the error detected in step 51 is recognized as a hardware error.

Step 57: The input/output processing program on the CPU 1 is executed at the time of channel activation and input/output internal! ((10) Since it is started at the end interrupt from 4, it is determined whether the input/output processing is for channel startup. If it is for channel startup, the process moves to step 58; If not, it means finalization processing, so the error recognition processing is ended.

Step 58: Since the software is operating normally, it issues a channel command to the input/output device (Ilo) 4 and waits for an end interrupt.

In this way, in the present invention, hardware errors,
Or in any case of a microprogram detection error, when the error occurs, do not display the cause of the error, just set the ERR bit to ``1'' in the AST of the ACR31 in the car, and then is the channel (CH
) When AERR 3 is started, if AERR is 1, the cause of the error is set in the control register that sets command start information, and when the input/output processing program, that is, software is started on the CPU I side, the above AER
If it is R.1, issue a NOP command and
When the command ends normally, the AERR=1 is recognized as a microprogram detection error and the contents of the control register are logged, but if the NOP command does not end normally, it is recognized as a hardware error. There is a characteristic in the place where it is made.

〔Effect of the invention〕

As explained above in detail, the error cause display method of the present invention is based on the microprogram executed by the processor (MPU).
11), the error detected by the hardware.

Displays a channel error (AERR) in a specific bit of the status register (AsT) by outputting a logical sum with the error bit detected by the above microprogram,
When the above microprogram is started, if the channel error (AERR) is “1”, the channel (C
) The cause of the error held in the work memory in l) is displayed in the control register, and the cause of the error held in the work memory in
When the input/output processing program executed in the central processing unit (CPU) that controls the The contents of the control register mentioned above are logged as a microprogram error, and when the NOP command does not complete normally and times out, it is recognized as a hardware error.
) only needs one bit to display the error, which speeds up error detection.In addition, the detailed cause required when a microprogram detection error occurs is displayed in the existing control register, eliminating the need for a dedicated display register. This has the effect of significantly reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an error cause display method according to the present invention. FIG. 2 is a diagram showing the configuration of a computer system to which the present invention is applied. FIG. 3 is a diagram showing means for displaying and recognizing the cause of an error by implementing the present invention. FIG. 4 is a diagram showing an example of a conventional error cause display method. It is. In the drawing, 1 is the central processing unit (CPU), 2 is the main memory (MM)
. 3 is the channel (CH), 4 is the input/output device (Ilo
). 31 is a channel control register (^CR). 32 is a processor (MPU), 33 is a control memory (
CS). 34 is a random access memory (RAM). 40-46. and 50 to 58 are steps of error cause display and recognition means. AST is a status register in ACR31. AERR is the channel error bit in the AST; ABSY is the channel busy bit in the AST. DVA is device address. AOP is a channel command. are shown respectively.

Claims (1)

[Claims] Controlled by a microprogram executed by a processor (MPU) (32), a central processing unit (CP
U) The channel busy (A
Errors detected by the hardware and errors detected by the microprogram at the time the error occurs, regardless of whether the microprogram is running or not, on the channel (CH) (3) that displays The channel error (A
A first means in which the channel error (AERR) bit is "1" when the microprogram is started, the channel (CH) ( 3) a second means for displaying the cause of the error in the control register; and software for starting or terminating the channel (CH) (3) in the central processing unit (CPU) (1) is started. When the channel error (AERR) bit is “1”, a NOP command is issued and the NOP
A third means for logging and displaying the contents of the channel control register at the end of command execution is provided so that the cause of the error can be analyzed, and a third means is provided to log and display the contents of the channel control register at the end of the execution of the command. or the channel (CH) (3)
Channel error (AE) is displayed while busy (ABSY) is displayed.
An error cause display method characterized in that when the RR) bit is "1", it is recognized as a hardware error.