JPS6270942A - Test system for information processor - Google Patents

Abstract

PURPOSE:To ensure the test of an information processor with high efficiency with no intermission of test due to stall by executing a random test program on a simulator, and carrying out the test after confirming the absence of stalls. CONSTITUTION:A random test program 311 produced by a random test program producing part 310 is simulated by a simulator 32. Then it is checked whether or not a stall detecting part 322 of the simulator 32 detects the stall condition. When no stall condition is detected, a request is issued for execution of the program 311 loaded in a main storage 4 in a processor 2 for information to be tested. Thus it is possible to carry out the test of an information processor with high efficiency and with no intermission of the test due to a stall.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a testing method for an information processing device, and more particularly to a testing method for an information processing device using randomly generated test data and test procedures.

[Conventional technology]

Conventionally, this type of information processing device testing method has been based on the results of running a random test program consisting of test data and test procedures randomly generated using random numbers with advance control of the information processing device under test enabled. [Problems to be Solved by the Invention] The conventional testing method for information processing devices described above is based on the test data. and test procedures are generated using random numbers, so if the information processing device is tested with a logic error that causes a stall with specific test data or instruction combinations, it will stall frequently and data will not be collected each time. The disadvantage is that testing efficiency is poor because the test must be restarted.

In view of the above-mentioned points, an object of the present invention is to provide a testing method for an information processing device that can efficiently perform a test without interrupting the test due to a stall.

[Means for solving problems]

A testing method for an information processing device according to the present invention includes a simulator having the same instruction set as the information processing device under test, a random test program generation means for generating a random test program, and a simulator for starting the random test program in the simulator. a stall detecting means for detecting a stall in the simulator; and a second starting means for starting the random test program in the information processing device under test when the stall detecting means does not detect a stall in the simulator. a starting means for reading out the execution results of the random test program from the simulator and the information processing device under test; and a reading means for reading out the execution results of the random test program read from the simulator and the information processing device under test. and execution result comparison means for comparison.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a system configuration diagram of an embodiment of the present invention, which includes a first main memory 3 in which a random test program, a simulator including a stall detection section, etc. are stored, and a first instruction processing section 5 that executes the program. Test processing equipment with
and a second main memory 4 that stores a random test program.
and an information processing device under test 2 having a second instruction processing unit 6 that executes a program, and a device having data transfer and interprocessor communication functions between the test processing device 1 and the information processing device under test 2. It consists of an interface 7.

FIG. 2 shows the configuration of programs stored in the first main memory 3, and shows the configuration of the programs stored in the first main memory 3.
0, a test control program 31, and a simulator 32. The test control program 31 includes a random test program creation section 310 and a random test program 311.
The random test program 311 further includes random test data 3110 and a random test procedure 3111. Simulator 3
2 is a third main memory 320 and a third instruction processing unit 321;
and a stall detection section 322.

FIG. 3 shows the contents of the random test data 3110 in the random test program 311, which consists of a register data area and a memory data area.

FIG. 4 shows the contents of the random test procedure 3111, which consists of a load instruction group, a random test instruction group, a store instruction group, and a monitor call instruction.

5 and 6 show the flow of processing in the test control program 31.

FIG. 7 shows the flow of processing in the simulator 32.

FIG. 8 shows the information processing device under test 2 and the simulator 32.
The process flow of the monitor operating above is shown below.

Next, the operation of the test method for the information processing apparatus of this embodiment configured as described above will be explained.

First, the operating system 30 running on the test processing device 1 loads the test control program 31 and the simulator 32 into the first main memory 3, and starts the test control program 31 on the test processing device 1.

The activated test control program 31 sequentially executes the processes shown in FIG. 5 to test the information processing device 2 under test. First, the random test program creation unit 310 creates random test data 3110 using random numbers in process 50, and creates random test procedures 3111 in process 51 also using random numbers.

In addition, regarding the creation of random test procedure 3111, please refer to Part 6.
This will be explained in detail in the explanation of the figures. Subsequently, in process 52, the random test program 311 created by the random test program creation section 310 is transferred to the third main memory 320, and further transferred to the second main memory 4 via the inter-device interface 7. Next, in process 53, the simulator 32
and requests execution of the random test program 311 loaded into the third main memory 320. Note that the processing in the simulator 32 will be explained in detail in the explanation of FIG.

When the processing in the simulator 32 is completed and control is returned to the test control program 31, it is checked in process 54 whether or not the stall detection unit 322 of the simulator 32 has detected a stall condition. The process advances to step 59 to check the test termination request. On the other hand, processing 5
4, when a stall condition is not detected in step 55, the random test is loaded into the second main memory 4 in the information processing device under test 2 using the inter-processor communication function of the inter-device interface 7. Program 3
After requesting execution of step 11, it waits for a termination interrupt sent from the information processing device under test 2 via the inter-device interface 7.

The execution result comparison unit 312 that has received the end interrupt from the information processing device under test 2 transfers the execution result of the random test program 311 in the simulator 32 from the third main memory 320 to the information processing device under test 2 in step 56. The execution results are sent to the second device via the inter-device interface 7.
are read from the main memory 4 of each. Next, in process 57, the two execution results are compared, and if they match, it is checked in process 59 whether or not there is a test termination request, and if there is a test termination request, the test is terminated, and if there is no test termination request, it is checked. Returning to process 50, the test continues. On the other hand, if the execution results do not match in process 57, an error message is output to the printing device in process 58, and then a test termination request is detected in process 59.

Next, the process 51 for creating the random test procedure 3111 will be explained in more detail using FIG.

First, in the random test procedure 3, load commands for loading the test data created in the register data area in the random test data 3110 into the registers in process 60 are used.
Create at the beginning of 111. Next, in step 61, a random instruction code is determined using random numbers. However, if the instruction codes determined using random numbers are executed as they are, some instruction codes will be included that make it impossible to successfully execute the subsequent random test procedure, so the validity of the instruction codes is checked in step 62. However, if the instruction code is invalid, the process returns to step 61 and determines the instruction code again. Once the instruction code is determined in this way, in step 63, random numbers are used to determine operands according to the format of the instruction code. next,
In process 64, the validity of the operand is checked in the same way as the instruction code, and if it is invalid, the process returns to process 63. In particular, for instructions that access the main memory, the range of random numbers is limited so that the random test data 3110 can be accessed. When the instruction words for one instruction are stored in the random test instruction group of the random test procedure 3111 in this way, processing 6
In Step 5, the number of created random test instructions is checked, and if it is less than the predetermined number, the process returns to Step 61 and the next instruction is created. After all the specified number of instructions have been created, in process 66 a group of store instructions for storing the register contents in the register data area of the random test data 3110 is created in the random test procedure 3111. Therefore, all the execution results of the random test program 311 will be stored in the random test data 3110 area. Finally, in step 67, a monitor call command for notifying the monitor of the end of the random test program 31 is created in the random test procedure 3111, and the creation process of the random test procedure 3111 is ended.

Next, the processing in the simulator 32 will be explained using FIG. 7.

When the simulator 32 is activated, it simulates inter-processor communication side interaction in process 71. Next, in process 72, an instruction word is retrieved from the third main memory 320, and in process 73, it is checked whether the retrieved instruction word is an instruction for inter-processor communication. If it is an instruction for inter-processor communication, the processing in the simulator 32 is finished, and if it is another instruction, the instruction word is sent to the processor detection unit 32 in process 74.
In step 2, a stall condition is checked, and when a stall condition is detected, the stall condition detection is registered in step 75, and the process ends.

On the other hand, if no stall condition is detected in process 74, processing according to the instruction word is performed in process 76, and
After updating the instruction counter in step 7, the process returns to step 72.

In this manner, simulator 32 processes instructions sequentially until an interprocessor communication instruction appears or until a stall condition is detected.

Subsequently, the information processing device under test 2 and the simulator 32
The eighth section describes the processing on the monitor that is preloaded into the computer and controls the execution of the random test program 311.
This will be explained using figures.

First, when the monitor operates on the information processing device under test 2, the Ridum test program 3 notified in process 53
Process 80 waits for a start request No. 11, that is, an inter-processor communication side request. When the interrupt is accepted, the random test program 311 is activated in process 81 and a test is executed.

The end of the test is notified to the monitor as a monitor call interrupt by executing the monitor call instruction created at the end of the random test procedure 3111. The monitor waits for a monitor call interrupt in process 82, and when the interrupt is accepted, random test program 3 is executed in process 83.
11 is executed to notify the test processing device l of the completion of step 11. Furthermore, the monitor returns to process 80 to wait for a request to start the newly created random test program 311.

On the other hand, when executing the monitor on the simulator 32,
A process 80 detects the inter-processor communication side interference caused by the process 71, and a process 81 starts the random test program 311. To end the test, the inter-processor communication command executed in step 83 is detected in step 73 of the simulator 32, and the test control program 31 is notified when the simulator 32 ends.

〔Effect of the invention〕

As explained above, the present invention executes a random test program on a simulator that has the same instruction set as the information processing device under test, and executes it on the information processing device under test after confirming that it will not stall. This has the effect of allowing efficient testing without interruption.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the test method of the information processing device of the present invention, FIG. 2 is a program configuration diagram in the first main memory shown in FIG. 1, and FIG. 3 is a random test. Data configuration diagram, Figure 4 is a configuration diagram of the random test procedure, Figures 5 and 6 are flowcharts showing the processing in the test control program, Figure 7 is a flowchart showing the processing in the simulator, and Figure 8 is a flowchart showing the processing in the monitor. It is a flow chart showing processing. In the figure, ■...Test processing device, 2... Information processing device under test, 3... First main memory, 4... Second main memory, 5... First instruction processing Part, 6... Second instruction processing unit, 7... Inter-device interface, 30... Operating system, 31... Test control program, 32... Simulator, 310... Random test program creation Part, 31
1...Random test program, 312...
- Execution result comparison unit, 320...Third main memory, 321...Third instruction processing unit, 322...Stall detection unit, 3110...Random test data, 3111...Random This is a test procedure. Agent Patent Attorney Susumu Uchihara Figure 3 Figure 4 Figure 6 Figure 7

Claims (1)

[Scope of Claims] A simulator having the same instruction set as the information processing device under test; random test program generating means for generating a random test program; first starting means for starting the random test program in the simulator; a stall detection means for detecting a stall in the simulator; a second starting means for starting the random test program on the information processing device under test when the stall detection means does not detect a stall in the simulator; reading means for reading the execution results of the random test program from the simulator and the information processing device under test; and execution result comparing means for comparing the execution results of the random test program read from the simulator and the information processing device under test. A testing method for an information processing device, comprising: